Lines Matching refs:PhysReg
87 MCPhysReg PhysReg = 0; ///< Currently held here.
140 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
143 void markRegUsedInInstr(MCPhysReg PhysReg) {
144 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
149 bool isRegUsedInInstr(MCPhysReg PhysReg) const {
150 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
198 void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg,
200 unsigned calcSpillCost(MCPhysReg PhysReg) const;
201 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg);
218 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
227 MCPhysReg PhysReg);
242 void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
243 PhysRegState[PhysReg] = NewState;
342 /// Insert reload instruction for \p PhysReg before \p Before.
344 MCPhysReg PhysReg) {
346 << printReg(PhysReg, TRI) << '\n');
349 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI);
373 if (MO.getReg() == LR.PhysReg)
390 assert(PhysRegState[LR.PhysReg] == LR.VirtReg &&
392 setPhysRegState(LR.PhysReg, regFree);
393 LR.PhysReg = 0;
401 if (LRI != LiveVirtRegs.end() && LRI->PhysReg)
412 assert(LRI != LiveVirtRegs.end() && LRI->PhysReg &&
419 assert(PhysRegState[LR.PhysReg] == LR.VirtReg && "Broken RegState mapping");
427 spill(MI, LR.VirtReg, LR.PhysReg, SpillKill);
442 if (!LR.PhysReg)
459 Register PhysReg = MO.getReg();
460 assert(PhysReg.isPhysical() && "Bad usePhysReg operand");
462 markRegUsedInInstr(PhysReg);
463 switch (PhysRegState[PhysReg]) {
467 PhysRegState[PhysReg] = regFree;
479 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
485 // Either PhysReg is a subregister of Alias and we mark the
486 // whole register as free, or PhysReg is the superregister of
488 // PhysReg.
489 // In the latter case, since PhysReg was disabled, this means that
494 assert((TRI->isSuperRegister(PhysReg, Alias) ||
495 TRI->isSuperRegister(Alias, PhysReg)) &&
499 if (TRI->isSuperRegister(PhysReg, Alias)) {
514 setPhysRegState(PhysReg, regFree);
518 /// Mark PhysReg as reserved or free after spilling any virtregs. This is very
522 MCPhysReg PhysReg, RegState NewState) {
523 markRegUsedInInstr(PhysReg);
524 switch (Register VirtReg = PhysRegState[PhysReg]) {
532 setPhysRegState(PhysReg, NewState);
537 setPhysRegState(PhysReg, NewState);
538 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
549 if (TRI->isSuperRegister(PhysReg, Alias))
556 /// Return the cost of spilling clearing out PhysReg and aliases so it is free
557 /// for allocation. Returns 0 when PhysReg is free or disabled with all aliases
559 /// \returns spillImpossible when PhysReg or an alias can't be spilled.
560 unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
561 if (isRegUsedInInstr(PhysReg)) {
562 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI)
566 switch (Register VirtReg = PhysRegState[PhysReg]) {
573 << printReg(PhysReg, TRI) << " is reserved already.\n");
577 assert(LRI != LiveVirtRegs.end() && LRI->PhysReg &&
584 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n");
586 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
598 assert(LRI != LiveVirtRegs.end() && LRI->PhysReg &&
608 /// This method updates local state so that we know that PhysReg is the
611 void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) {
614 << printReg(PhysReg, TRI) << '\n');
615 assert(LR.PhysReg == 0 && "Already assigned a physreg");
616 assert(PhysReg != 0 && "Trying to assign no register");
617 LR.PhysReg = PhysReg;
618 setPhysRegState(PhysReg, VirtReg);
717 for (MCPhysReg PhysReg : AllocationOrder) {
718 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
719 unsigned Cost = calcSpillCost(PhysReg);
723 assignVirtToPhysReg(LR, PhysReg);
727 if (PhysReg == Hint1 || PhysReg == Hint0)
731 BestReg = PhysReg;
758 MCPhysReg PhysReg;
759 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
760 PhysReg = LRI->PhysReg;
765 PhysReg = AllocationOrder[0];
770 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
773 MO.setReg(PhysReg);
784 if (!LRI->PhysReg) {
800 assert(LRI->PhysReg && "Register not assigned");
804 markRegUsedInInstr(LRI->PhysReg);
805 return LRI->PhysReg;
818 if (!LRI->PhysReg) {
820 reload(MI, VirtReg, LRI->PhysReg);
846 assert(LRI->PhysReg && "Register not assigned");
849 markRegUsedInInstr(LRI->PhysReg);
853 /// Changes operand OpNum in MI the refer the PhysReg, considering subregs. This
857 MCPhysReg PhysReg) {
860 MO.setReg(PhysReg);
866 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
873 MI.addRegisterKilled(PhysReg, TRI, true);
880 MI.addRegisterDefined(PhysReg, TRI);
932 MCPhysReg PhysReg = LR.PhysReg;
933 setPhysReg(MI, MO, PhysReg);
941 PartialDefs.push_back(LR.PhysReg);
955 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, 0);
956 if (setPhysReg(MI, MI.getOperand(I), PhysReg))
991 assert(LRI != LiveVirtRegs.end() && LRI->PhysReg &&
995 assert(LRI->PhysReg == Reg && "Bad inverse map");
1004 if (!i->PhysReg)
1007 assert(Register::isPhysicalRegister(i->PhysReg) && "Bad map value");
1008 assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
1113 MCPhysReg PhysReg = LR.PhysReg;
1114 CopySrcReg = (CopySrcReg == Reg || CopySrcReg == PhysReg) ? PhysReg : 0;
1115 if (setPhysReg(MI, MO, PhysReg))
1188 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg);
1189 if (setPhysReg(MI, MI.getOperand(I), PhysReg)) {
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0;
1225 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1226 setPhysReg(MI, MO, LRI->PhysReg);
1257 if (MRI->isAllocatable(LI.PhysReg))
1258 definePhysReg(MII, LI.PhysReg, regReserved);