/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTLSDynamicCall.cpp | 82 unsigned Opc1, Opc2; local 89 Opc1 = PPC::ADDItlsgdL; 93 Opc1 = PPC::ADDItlsldL; 97 Opc1 = PPC::ADDItlsgdL32; 101 Opc1 = PPC::ADDItlsldL32; 117 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
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H A D | PPCISelDAGToDAG.cpp | 5351 unsigned Opc1, Opc2, Opc3; local 5355 Opc1 = PPC::VSPLTISB; 5360 Opc1 = PPC::VSPLTISH; 5366 Opc1 = PPC::VSPLTISW; 5380 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 5392 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 5394 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 5406 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); 5408 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.h | 56 MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, 60 MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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H A D | Mips16ISelLowering.cpp | 571 Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, argument 609 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB); 636 Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2, argument 675 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
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/freebsd-13-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
H A D | ContainerModeling.cpp | 140 BinaryOperator::Opcode Opc1, 974 BinaryOperator::Opcode Opc1, 978 return compare(State, Pos.getOffset(), Offset1, Opc1) &&
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineVectorOps.cpp | 1619 BinaryOperator::BinaryOps Opc1 = B1->getOpcode(); local 1621 if (ConstantsAreOp1 && Opc0 != Opc1) { 1625 if (Opc0 == Instruction::Shl || Opc1 == Instruction::Shl) 1633 Opc1 = AltB1.Opcode; 1638 if (Opc0 != Opc1)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIInstrInfo.cpp | 115 unsigned Opc1 = N1->getMachineOpcode(); local 118 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName); 163 unsigned Opc1 = Load1->getMachineOpcode(); local 166 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad()) 169 if (isDS(Opc0) && isDS(Opc1)) { 183 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset); 192 Offset1Idx -= get(Opc1).NumDefs; 198 if (isSMRD(Opc0) && isSMRD(Opc1)) { 201 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1) 224 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBU [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 6436 unsigned Opc1 = Load1->getMachineOpcode(); local 6438 switch (Opc1) { 6637 unsigned Opc1 = Load1->getMachineOpcode(); local 6639 if (Opc1 != Opc2) 6642 switch (Opc1) {
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H A D | X86ISelLowering.cpp | 24396 // (IntrData->Opc1 != 0), then we check the rounding mode operand. 24397 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; 24418 Opc = IntrData->Opc1; 24429 // (IntrData->Opc1 != 0), then we check the rounding mode operand. 24430 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; 24452 Opc = IntrData->Opc1; 24467 // (IntrData->Opc1 != 0), then we check the rounding mode operand. 24468 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; 24493 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1; 24519 Opc = IntrData->Opc1; [all...] |
H A D | X86IntrinsicsInfo.h | 47 uint16_t Opc1; member in struct:llvm::IntrinsicData
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H A D | X86ISelDAGToDAG.cpp | 3944 unsigned Opc1 = N->getOpcode(); local 3969 switch (Opc1) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 419 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; local 424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
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/freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 6578 Value *Opc1 = EmitScalarExpr(E->getArg(1)); 6587 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); 6605 Value *Opc1 = EmitScalarExpr(E->getArg(1)); 6607 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm});
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