| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMemoryLegalizer.cpp | 413 bool expandLoad(const SIMemOpInfo &MOI,
417 bool expandStore(const SIMemOpInfo &MOI,
421 bool expandAtomicFence(const SIMemOpInfo &MOI,
425 bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI,
1148 bool SIMemoryLegalizer::expandLoad(const SIMemOpInfo &MOI, argument
1154 if (MOI.isAtomic()) {
1155 if (MOI.getOrdering() == AtomicOrdering::Monotonic ||
1156 MOI.getOrdering() == AtomicOrdering::Acquire ||
1157 MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) {
1158 Changed |= CC->enableLoadCacheBypass(MI, MOI
1193 expandStore(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument
1220 expandAtomicFence(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument
1258 expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument
[all...] |
| H A D | R600EmitClauseMarkers.cpp | 201 MOI = Def->operands_begin(),
202 MOE = Def->operands_end(); MOI != MOE; ++MOI) {
203 if (!MOI->isReg() || !MOI->isDef() ||
204 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
228 if (UseI->readsRegister(MOI->getReg(), &TRI))
232 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | StackMaps.cpp | 102 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, argument
106 if (MOI->isImm()) {
107 switch (MOI->getImm()) {
116 Register Reg = (++MOI)->getReg();
117 int64_t Imm = (++MOI)->getImm();
123 int64_t Size = (++MOI)->getImm();
125 Register Reg = (++MOI)->getReg();
126 int64_t Imm = (++MOI)->getImm();
132 ++MOI;
133 assert(MOI
297 recordStackMapOpers(const MCSymbol &MILabel, const MachineInstr &MI, uint64_t ID, MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, bool recordResult) argument
377 auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx()); local
[all...] |
| H A D | LiveRangeEdit.cpp | 309 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
310 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
311 if (!MOI->isReg())
313 Register Reg = MOI->getReg();
316 if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
318 else if (MOI->isDef())
328 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
329 (MOI->readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, *MOI))))
[all...] |
| H A D | VirtRegMap.cpp | 507 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
508 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
509 MachineOperand &MO = *MOI;
|
| H A D | LiveInterval.cpp | 904 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
905 if (!MOI->isReg() || !MOI->isDef())
907 if (MOI->getReg() != Reg)
909 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg());
|
| H A D | MachineVerifier.cpp | 2557 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2558 if (!MOI->isReg() || !MOI->isDef())
2561 if (MOI->getReg() != Reg)
2564 if (!Register::isPhysicalRegister(MOI->getReg()) ||
2565 !TRI->hasRegUnit(MOI->getReg(), Reg))
2569 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2572 if (MOI
[all...] |
| H A D | MachineTraceMetrics.cpp | 900 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
902 MOI != MOE; ++MOI) {
903 const MachineOperand &MO = *MOI;
910 ReadOps.push_back(MI.getOperandNo(MOI));
923 DepHeight += SchedModel.computeOperandLatency(&MI, MI.getOperandNo(MOI),
|
| H A D | LiveIntervals.cpp | 1653 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
1655 MOI != MOE; ++MOI) {
1656 if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
1657 !hasInterval(MOI->getReg())) {
1658 createAndComputeVirtRegInterval(MOI->getReg());
|
| H A D | ModuloSchedule.cpp | 726 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
728 MOI != MOE; ++MOI) {
729 if (!MOI->isReg() || !MOI->isDef())
731 Register reg = MOI->getReg();
734 used = !MOI->isDead();
|
| H A D | MachinePipeliner.cpp | 840 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
842 MOI != MOE; ++MOI) {
843 if (!MOI->isReg())
845 Register Reg = MOI->getReg();
846 if (MOI->isDef()) {
868 } else if (MOI->isUse()) {
878 ST.adjustSchedDependency(SU, 0, &I, MI->getOperandNo(MOI), Dep);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/ |
| H A D | AVRInstPrinter.cpp | 103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo]; local
104 if (MOI.RegClass == AVR::ZREGRegClassID) {
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) ||
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) ||
126 (MOI.RegClass == AVR::ZREGRegClassID);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | StackMaps.h | 329 parseOperand(MachineInstr::const_mop_iterator MOI,
350 MachineInstr::const_mop_iterator MOI,
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 724 MachineInstr::mop_iterator MOI = MI->operands_begin(); local
726 MIB.add(*MOI);
727 ++MOI;
730 for (const MachineOperand &MO : make_range(MOI, MI->operands_end()))
|