Searched refs:Hexagon (Results 1 - 25 of 65) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_112d30d6:
22 case Hexagon::Sched::tc_151bf368:
23 case Hexagon::Sched::tc_1c2c7a4a:
24 case Hexagon::Sched::tc_1d41f8b7:
25 case Hexagon::Sched::tc_23708a21:
26 case Hexagon::Sched::tc_24f426ab:
27 case Hexagon::Sched::tc_2f573607:
28 case Hexagon::Sched::tc_388f9897:
29 case Hexagon::Sched::tc_3d14a17b:
30 case Hexagon
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H A DHexagonDepArch.h20 namespace Hexagon { namespace in namespace:llvm
36 {"generic", Hexagon::ArchEnum::V60},
37 {"hexagonv5", Hexagon::ArchEnum::V5},
38 {"hexagonv55", Hexagon::ArchEnum::V55},
39 {"hexagonv60", Hexagon::ArchEnum::V60},
40 {"hexagonv62", Hexagon::ArchEnum::V62},
41 {"hexagonv65", Hexagon::ArchEnum::V65},
42 {"hexagonv66", Hexagon::ArchEnum::V66},
43 {"hexagonv67", Hexagon::ArchEnum::V67},
44 {"hexagonv67t", Hexagon
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H A DHexagonRegisterInfo.cpp1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
15 #include "Hexagon.h"
45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon
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H A DHexagonInstrInfo.cpp1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
14 #include "Hexagon.h"
102 /// Constants for Hexagon instructions.
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
129 (Reg >= Hexagon::R16 && Reg <= Hexagon
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H A DHexagonAsmPrinter.cpp1 //===- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ---===//
10 // of machine-dependent LLVM code to Hexagon assembly language. This printer is
16 #include "Hexagon.h"
68 assert(Hexagon::IntRegsRegClass.contains(Reg));
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
137 Hexagon::isub_lo :
138 Hexagon::isub_hi);
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8;
277 case Hexagon
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H A DHexagonNewValueJump.cpp1 //===- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -----------===//
9 // This implements NewValueJump pass in Hexagon.
24 #include "Hexagon.h"
86 StringRef getPassName() const override { return "Hexagon NewValueJump"; }
110 "Hexagon NewValueJump", false, false)
113 "Hexagon NewValueJump", false, false)
157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
226 // The following pseudo Hexagon instructions sets "use" and "def"
230 if (MII->getOpcode() == Hexagon::LDriw_pred ||
231 MII->getOpcode() == Hexagon
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H A DHexagonCFGOptimizer.cpp9 #include "Hexagon.h"
48 StringRef getPassName() const override { return "Hexagon CFG Optimizer"; }
63 case Hexagon::J2_jumpt:
64 case Hexagon::J2_jumptpt:
65 case Hexagon::J2_jumpf:
66 case Hexagon::J2_jumpfpt:
67 case Hexagon::J2_jumptnew:
68 case Hexagon::J2_jumpfnew:
69 case Hexagon::J2_jumptnewpt:
70 case Hexagon
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H A DHexagonVectorPrint.cpp64 StringRef getPassName() const override { return "Hexagon VectorPrint pass"; }
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) ||
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) ||
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) ||
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);
81 if (R >= Hexagon
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H A DHexagonSubtarget.h1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
66 Hexagon::ArchEnum HexagonArchVersion;
67 Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch;
141 return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;
144 return getHexagonArchVersion() == Hexagon::ArchEnum::V5;
147 return getHexagonArchVersion() >= Hexagon::ArchEnum::V55;
150 return getHexagonArchVersion() == Hexagon::ArchEnum::V55;
153 return getHexagonArchVersion() >= Hexagon
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H A DHexagonConstExtenders.cpp225 return "Hexagon constant-extender optimization";
571 "Hexagon constant-extender optimization", false, false)
574 "Hexagon constant-extender optimization", false, false)
801 case Hexagon::S4_storeirbt_io:
802 case Hexagon::S4_storeirbf_io:
803 case Hexagon::S4_storeirht_io:
804 case Hexagon::S4_storeirhf_io:
805 case Hexagon::S4_storeirit_io:
806 case Hexagon::S4_storeirif_io:
807 case Hexagon
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H A DHexagonGenPredicate.cpp91 return "Hexagon generate predicate operations";
131 "Hexagon generate predicate operations", false, false)
134 "Hexagon generate predicate operations", false, false)
140 return RC == &Hexagon::PredRegsRegClass;
144 using namespace Hexagon;
197 case Hexagon::C2_cmpeqi:
198 case Hexagon::C4_cmpneqi:
213 case Hexagon::C2_tfrpr:
258 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) {
268 const TargetRegisterClass *PredRC = &Hexagon
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H A DHexagonMachineFunctionInfo.h1 //=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
17 namespace Hexagon { namespace in namespace:llvm
22 } // end namespace Hexagon
24 /// Hexagon target-specific information for each MachineFunction.
62 PacketInfo[MI] |= Hexagon::StartPacket;
65 PacketInfo[MI] |= Hexagon::EndPacket;
69 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
73 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
H A DHexagonFixupHwLoops.cpp14 #include "Hexagon.h"
53 return "Hexagon Hardware Loop Fixup";
77 "Hexagon Hardware Loops Fixup", false, false)
85 return MI.getOpcode() == Hexagon::J2_loop0r ||
86 MI.getOpcode() == Hexagon::J2_loop0i ||
87 MI.getOpcode() == Hexagon::J2_loop1r ||
88 MI.getOpcode() == Hexagon::J2_loop1i;
97 /// For Hexagon, if the loop label is to far from the
176 case Hexagon::J2_loop0r:
177 newOp = Hexagon
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H A DHexagonFrameLowering.h1 //==- HexagonFrameLowering.h - Define frame lowering for Hexagon -*- C++ -*-==//
12 #include "Hexagon.h"
92 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
93 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
94 { Hexagon::R21, -20 }, { Hexagon
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H A DHexagonSplitConst32AndConst64.cpp46 return "Hexagon Split Const32s and Const64s";
59 "Hexagon Split Const32s and Const64s", false, false)
78 if (Opc == Hexagon::CONST32) {
82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
85 } else if (Opc == Hexagon::CONST64) {
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
97 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
H A DHexagonVExtract.cpp12 #include "Hexagon.h"
46 return "Hexagon optimize vextract";
65 "Hexagon optimize vextract", false, false)
71 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
79 if (DI->getOpcode() == Hexagon::A2_tfrsi) {
83 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
90 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
91 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
94 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
116 if (Opc != Hexagon
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H A DHexagonRDFOpt.cpp68 return "Hexagon RDF optimizations";
106 "Hexagon RDF optimizations", false, false)
110 "Hexagon RDF optimizations", false, false)
120 case Hexagon::A2_combinew: {
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
131 case Hexagon::A2_addi: {
137 case Hexagon::A2_tfr: {
226 case Hexagon::L2_loadri_pi:
227 NewOpc = Hexagon
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H A DHexagonCopyToCombine.cpp1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
80 return "Hexagon Copy-To-Combine Pass";
125 "Hexagon Copy-To-Combine Pass", false, false)
130 case Hexagon::A2_tfr: {
138 return Hexagon::IntRegsRegClass.contains(DestReg) &&
139 Hexagon::IntRegsRegClass.contains(SrcReg);
142 case Hexagon::A2_tfrsi: {
158 return Hexagon::IntRegsRegClass.contains(DestReg) &&
162 case Hexagon::V6_vassign:
173 if (I.getOpcode() == Hexagon
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H A DHexagonPeephole.cpp1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
36 #include "Hexagon.h"
95 return "Hexagon optimize redundant zero and size extends";
106 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
135 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
153 if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
170 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
180 std::make_pair(*&SrcReg, Hexagon::isub_hi);
184 if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
208 if (Src.getSubReg() != Hexagon
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp1 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
36 using namespace Hexagon;
42 /// Hexagon disassembler for all Hexagon platforms.
173 MI.setOpcode(Hexagon::BUNDLE);
203 case Hexagon::S2_allocframe:
204 if (MI.getOperand(0).getReg() == Hexagon::R29) {
205 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
210 case Hexagon::L2_deallocframe:
211 if (MI.getOperand(0).getReg() == Hexagon
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp30 using namespace Hexagon;
200 case Hexagon::L2_loadri_io:
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
217 case Hexagon::L2_loadrub_io:
237 case Hexagon::L2_loadrh_io:
238 case Hexagon::L2_loadruh_io:
248 case Hexagon::L2_loadrb_io:
258 case Hexagon::L2_loadrd_io:
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg &&
269 case Hexagon
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H A DHexagonMCCompound.cpp1 //=== HexagonMCCompound.cpp - Hexagon Compound checker -------------------===//
25 using namespace Hexagon;
91 case Hexagon::C2_cmpeq:
92 case Hexagon::C2_cmpgt:
93 case Hexagon::C2_cmpgtu:
99 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
104 case Hexagon::C2_cmpeqi:
105 case Hexagon::C2_cmpgti:
106 case Hexagon
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H A DHexagonMCInstrInfo.cpp1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
36 return Register != Hexagon::NoRegister;
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
71 MCInst const &Hexagon::PacketIterator::operator*() const {
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
102 iterator_range<Hexagon
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H A DHexagonMCChecker.h10 // packet constraint rules of the Hexagon ISA.
106 return (Hexagon::P0 == R || Hexagon::P1 == R || Hexagon::P2 == R ||
107 Hexagon::P3 == R);
111 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
112 Hexagon::LC1 == R);
H A DHexagonMCChecker.cpp10 // packet constraint rules of the Hexagon ISA.
35 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
39 ReadOnly.insert(Hexagon::PC);
40 ReadOnly.insert(Hexagon::C9_8);
44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0?
45 Defs[Hexagon::LC0].insert(Unconditional);
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0?
49 Defs[Hexagon::LC1].insert(Unconditional);
91 unsigned PredReg = Hexagon::NoRegister;
106 if (Hexagon
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