Lines Matching refs:Hexagon
1 //===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
9 // This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
36 return Register != Hexagon::NoRegister;
39 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
45 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
50 Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
71 MCInst const &Hexagon::PacketIterator::operator*() const {
77 bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
102 iterator_range<Hexagon::PacketIterator>
106 return make_range(Hexagon::PacketIterator(MCII, MCI),
107 Hexagon::PacketIterator(MCII, MCI, nullptr));
139 if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
191 XMI.setOpcode(Hexagon::A4_ext);
206 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
254 using namespace Hexagon;
383 static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
415 /// Return the Hexagon ISA class for the insn.
533 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
557 (MCI.getOpcode() != Hexagon::C4_addipc))
605 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
606 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
636 return MCI.getOpcode() == Hexagon::A4_ext;
646 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
650 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
651 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
680 return (VecReg >= Hexagon::W0 && VecReg <= Hexagon::W15) ||
681 (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
685 return (VecReg >= Hexagon::WR0 && VecReg <= Hexagon::WR15);
689 return (VecReg >= Hexagon::V0 && VecReg <= Hexagon::V31);
699 2 * (IsRev ? VecRegPair - Hexagon::WR0 : VecRegPair - Hexagon::W0);
709 ? Producer - Hexagon::WR0
710 : Producer - Hexagon::W0;
711 const unsigned ConsumerSingleIndex = (Consumer - Hexagon::V0) >> 1;
749 auto &PredRegClass = MRI.getRegClass(Hexagon::PredRegsRegClassID);
758 Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID;
798 case Hexagon::SA1_addi:
799 case Hexagon::SA1_addrx:
800 case Hexagon::SA1_addsp:
801 case Hexagon::SA1_and1:
802 case Hexagon::SA1_clrf:
803 case Hexagon::SA1_clrfnew:
804 case Hexagon::SA1_clrt:
805 case Hexagon::SA1_clrtnew:
806 case Hexagon::SA1_cmpeqi:
807 case Hexagon::SA1_combine0i:
808 case Hexagon::SA1_combine1i:
809 case Hexagon::SA1_combine2i:
810 case Hexagon::SA1_combine3i:
811 case Hexagon::SA1_combinerz:
812 case Hexagon::SA1_combinezr:
813 case Hexagon::SA1_dec:
814 case Hexagon::SA1_inc:
815 case Hexagon::SA1_seti:
816 case Hexagon::SA1_setin1:
817 case Hexagon::SA1_sxtb:
818 case Hexagon::SA1_sxth:
819 case Hexagon::SA1_tfr:
820 case Hexagon::SA1_zxtb:
821 case Hexagon::SA1_zxth:
822 case Hexagon::SL1_loadri_io:
823 case Hexagon::SL1_loadrub_io:
824 case Hexagon::SL2_deallocframe:
825 case Hexagon::SL2_jumpr31:
826 case Hexagon::SL2_jumpr31_f:
827 case Hexagon::SL2_jumpr31_fnew:
828 case Hexagon::SL2_jumpr31_t:
829 case Hexagon::SL2_jumpr31_tnew:
830 case Hexagon::SL2_loadrb_io:
831 case Hexagon::SL2_loadrd_sp:
832 case Hexagon::SL2_loadrh_io:
833 case Hexagon::SL2_loadri_sp:
834 case Hexagon::SL2_loadruh_io:
835 case Hexagon::SL2_return:
836 case Hexagon::SL2_return_f:
837 case Hexagon::SL2_return_fnew:
838 case Hexagon::SL2_return_t:
839 case Hexagon::SL2_return_tnew:
840 case Hexagon::SS1_storeb_io:
841 case Hexagon::SS1_storew_io:
842 case Hexagon::SS2_allocframe:
843 case Hexagon::SS2_storebi0:
844 case Hexagon::SS2_storebi1:
845 case Hexagon::SS2_stored_sp:
846 case Hexagon::SS2_storeh_io:
847 case Hexagon::SS2_storew_sp:
848 case Hexagon::SS2_storewi0:
849 case Hexagon::SS2_storewi1:
903 const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
916 Nop.setOpcode(Hexagon::A2_nop);
931 if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
951 const bool IsTiny = STI.getFeatureBits() [Hexagon::ProcTinyCore];
952 const bool NoSlotReqd = Hexagon::A4_ext == OpCode ||
953 (IsTiny && Hexagon::A2_nop == OpCode) ||
954 (IsTiny && Hexagon::J4_hintjumpr == OpCode);
1014 return (Consumer - Hexagon::V0) & 0x1;
1015 if (Producer2 != Hexagon::NoRegister)