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  • only in /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/

Lines Matching refs:Hexagon

1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
9 // This file contains the Hexagon implementation of the TargetRegisterInfo
15 #include "Hexagon.h"
45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
57 using namespace Hexagon;
109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
111 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
117 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
120 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
138 Reserved.set(Hexagon::R29);
139 Reserved.set(Hexagon::R30);
140 Reserved.set(Hexagon::R31);
141 Reserved.set(Hexagon::VTMP);
144 Reserved.set(Hexagon::GELR); // G0
145 Reserved.set(Hexagon::GSR); // G1
146 Reserved.set(Hexagon::GOSP); // G2
147 Reserved.set(Hexagon::G3); // G3
150 Reserved.set(Hexagon::SA0); // C0
151 Reserved.set(Hexagon::LC0); // C1
152 Reserved.set(Hexagon::SA1); // C2
153 Reserved.set(Hexagon::LC1); // C3
154 Reserved.set(Hexagon::P3_0); // C4
155 Reserved.set(Hexagon::USR); // C8
156 Reserved.set(Hexagon::PC); // C9
157 Reserved.set(Hexagon::UGP); // C10
158 Reserved.set(Hexagon::GP); // C11
159 Reserved.set(Hexagon::CS0); // C12
160 Reserved.set(Hexagon::CS1); // C13
161 Reserved.set(Hexagon::UPCYCLELO); // C14
162 Reserved.set(Hexagon::UPCYCLEHI); // C15
163 Reserved.set(Hexagon::FRAMELIMIT); // C16
164 Reserved.set(Hexagon::FRAMEKEY); // C17
165 Reserved.set(Hexagon::PKTCOUNTLO); // C18
166 Reserved.set(Hexagon::PKTCOUNTHI); // C19
167 Reserved.set(Hexagon::UTIMERLO); // C30
168 Reserved.set(Hexagon::UTIMERHI); // C31
172 Reserved.set(Hexagon::C8);
173 Reserved.set(Hexagon::USR_OVF);
183 Reserved.set(Hexagon::R19);
196 // Hexagon_TODO: Do we need to enforce this for Hexagon?
217 case Hexagon::PS_fia:
218 MI.setDesc(HII.get(Hexagon::A2_addi));
222 case Hexagon::PS_fi:
224 MI.setDesc(HII.get(Hexagon::A2_addi));
232 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
234 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
257 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())
259 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID();
260 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID();
297 return Hexagon::R31;
311 return Hexagon::R30;
316 return Hexagon::R29;
322 assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
324 static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
325 static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
326 static const unsigned WSub[] = { Hexagon::wsub_lo, Hexagon::wsub_hi };
329 case Hexagon::CtrRegs64RegClassID:
330 case Hexagon::DoubleRegsRegClassID:
332 case Hexagon::HvxWRRegClassID:
334 case Hexagon::HvxVQRRegClassID:
352 return &Hexagon::IntRegsRegClass;
356 return Hexagon::R6;