/freebsd-13-stable/bin/pax/ |
H A D | options.c | 101 FSUB fsub[] = { 194 FSUB tmp; 371 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, 372 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) { 378 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i) 1027 FSUB tmp; 1193 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub, 1194 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frm [all...] |
H A D | pax.h | 74 typedef struct fsub FSUB; typedef in typeref:struct:fsub
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H A D | extern.h | 185 extern FSUB fsub[]; 208 extern FSUB *frmt;
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H A D | pax.c | 75 FSUB *frmt = NULL; /* archive format type */
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H A D | ar_subs.c | 568 FSUB *orgfrmt;
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 343 FSUB, enumerator in enum:llvm::ISD::NodeType
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H A D | TargetLowering.h | 2430 case ISD::FSUB: 2674 /// ISD::FADD, ISD::FSUB, or an ISD::FMUL which will be distributed into an 2677 assert((N->getOpcode() == ISD::FADD || N->getOpcode() == ISD::FSUB ||
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 375 case ISD::FSUB: 753 case ISD::FSUB: 1289 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Node->getValueType(0))) { 1292 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB. 1293 return DAG.getNode(ISD::FSUB, DL, Node->getValueType(0), Zero,
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H A D | SelectionDAGBuilder.cpp | 3013 visitBinary(I, ISD::FSUB); 4794 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4931 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4948 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4954 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 4973 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 4979 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 4985 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 5027 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 5044 SDValue t3 = DAG.getNode(ISD::FSUB, d [all...] |
H A D | SelectionDAGDumper.cpp | 254 case ISD::FSUB: return "fsub";
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H A D | TargetLowering.cpp | 2750 case ISD::FSUB: 5796 if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT)) 5812 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegX, Y, Flags); 5821 SDValue N = DAG.getNode(ISD::FSUB, DL, VT, NegY, X, Flags); 5828 case ISD::FSUB: { 5843 return DAG.getNode(ISD::FSUB, DL, VT, Y, X, Flags); 6389 // TODO: Should any fast-math-flags be set for the FSUB? 6404 SDValue Val = DAG.getNode(ISD::FSUB, dl, SrcVT, Src, FltOfs); 6415 // TODO: Should any fast-math-flags be set for the FSUB? 6417 DAG.getNode(ISD::FSUB, d [all...] |
H A D | LegalizeFloatTypes.cpp | 123 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; 1199 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break; 2178 case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break; 2519 case ISD::FSUB: R = SoftPromoteHalfRes_BinOp(N); break;
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H A D | LegalizeDAG.cpp | 2421 Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 3219 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB. 3220 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 3327 case ISD::FSUB: { 4236 case ISD::FSUB: 4546 case ISD::FSUB:
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H A D | DAGCombiner.cpp | 1649 case ISD::FSUB: return visitFSUB(N); 12189 /// Try to perform FMA combining on a given FSUB node. 12245 // Note: Commutes FSUB operands. 12304 // Note: Commutes FSUB operands. 12577 if (X.getOpcode() == ISD::FSUB && (Aggressive || X->hasOneUse())) { 12644 if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) 12647 return DAG.getNode(ISD::FSUB, DL, VT, N0, NegN1, Flags); 12650 if (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) 12653 return DAG.getNode(ISD::FSUB, DL, VT, N1, NegN0, Flags); 12666 return DAG.getNode(ISD::FSUB, D [all...] |
H A D | LegalizeVectorTypes.cpp | 135 case ISD::FSUB: 915 case ISD::FSUB: 2785 case ISD::FSUB:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 215 { ISD::FSUB, MVT::v2f64, 2 }, // subpd 579 { ISD::FSUB, MVT::v8f64, 1 }, // Skylake from http://www.agner.org/ 583 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ 751 { ISD::FSUB, MVT::v4f64, 1 }, // Haswell from http://www.agner.org/ 752 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ 811 { ISD::FSUB, MVT::f64, 1 }, // Nehalem from http://www.agner.org/ 812 { ISD::FSUB, MVT::f32 , 1 }, // Nehalem from http://www.agner.org/ 813 { ISD::FSUB, MVT::v2f64, 1 }, // Nehalem from http://www.agner.org/ 814 { ISD::FSUB, MVT::v4f32, 1 }, // Nehalem from http://www.agner.org/ 894 { ISD::FSUB, MV [all...] |
H A D | X86IntrinsicsInfo.h | 918 X86_INTRINSIC_DATA(avx512_sub_pd_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND), 919 X86_INTRINSIC_DATA(avx512_sub_ps_512, INTR_TYPE_2OP, ISD::FSUB, X86ISD::FSUB_RND),
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H A D | X86ISelLowering.cpp | 533 setOperationAction(ISD::FSUB, VT, Custom); 691 setOperationAction(ISD::FSUB, MVT::f128, LibCall); 1967 setTargetDAGCombine(ISD::FSUB); 9293 if (Opcode != ISD::FADD && Opcode != ISD::FSUB) 9333 if (Opcode == ISD::FSUB) 9487 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break; 9671 else if (isHorizontalBinOpPart(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, 19613 Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 19682 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 19738 return DAG.getNode(ISD::FSUB, D [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetTransformInfo.cpp | 510 case ISD::FSUB:
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H A D | AMDGPUISelLowering.cpp | 327 setOperationAction(ISD::FSUB, MVT::f64, Expand); 487 setOperationAction(ISD::FSUB, VT, Expand); 564 setTargetDAGCombine(ISD::FSUB); 580 case ISD::FSUB: 2091 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul); 2196 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign); 2231 SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1611 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, 1715 setOperationAction(ISD::FSUB, MVT::f64, Expand); 1752 setOperationAction(ISD::FSUB, MVT::f64, Legal);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 133 setOperationAction(ISD::FSUB, MVT::f16, Promote); 396 setOperationAction(ISD::FSUB, Ty, Legal); 1924 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1719 setOperationAction(ISD::FSUB, MVT::f128, Legal); 1744 setOperationAction(ISD::FSUB, MVT::f128, Custom); 3046 case ISD::FSUB: return LowerF128Op(Op, DAG,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1802 case ISD::FSUB: 2852 return SelectBinaryFPOp(I, ISD::FSUB);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1012 setOperationAction(ISD::FSUB, MVT::f128, Legal); 1086 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 1137 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 8169 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); 8179 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); 8185 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); 8191 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); 8197 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); 8334 // TODO: Are there fast-math-flags to propagate to this FSUB? 8335 SDValue True = DAG.getNode(ISD::FSUB, d [all...] |