Lines Matching refs:FSUB
533 setOperationAction(ISD::FSUB, VT, Custom);
691 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
1967 setTargetDAGCombine(ISD::FSUB);
9293 if (Opcode != ISD::FADD && Opcode != ISD::FSUB)
9333 if (Opcode == ISD::FSUB)
9487 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break;
9671 else if (isHorizontalBinOpPart(BV, ISD::FSUB, DAG, 0, NumElts, InVec0,
19613 Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
19682 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
19738 return DAG.getNode(ISD::FSUB, DL, MVT::v2f64, Or, VBias);
19808 return DAG.getNode(ISD::FSUB, DL, MVT::v4f64, Or, VBias);
19895 DAG.getNode(ISD::FSUB, DL, VecFloatVT, HighBitcast, VecCstFSub);
20158 Value = DAG.getNode(ISD::FSUB, DL, TheVT, Value, FltOfs);
21138 case ISD::FSUB: HOpcode = X86ISD::FHSUB; break;
29261 case ISD::FSUB: return lowerFaddFsub(Op, DAG);
29960 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
36328 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB ||
36590 // Make sure we have an FADD and an FSUB.
36591 if ((V1.getOpcode() != ISD::FADD && V1.getOpcode() != ISD::FSUB) ||
36592 (V2.getOpcode() != ISD::FADD && V2.getOpcode() != ISD::FSUB) ||
36603 if (V1.getOpcode() == ISD::FSUB) {
36609 assert(V2.getOpcode() == ISD::FSUB && "Unexpected opcode");
36879 // If we have legalized the vector types, look for blends of FADD and FSUB
39218 case ISD::FSUB:
44572 assert((IsFadd || N->getOpcode() == ISD::FSUB) && "Wrong opcode");
45071 /// or FSUB(0, x)
45120 case ISD::FSUB:
45127 // bits of Op1 are sign bit masks. For FSUB, we
45130 if (Opc == ISD::FSUB)
48904 case ISD::FSUB: return combineFaddFsub(N, DAG, Subtarget);