/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUSubtarget.h | 334 bool FMA; member in class:llvm::GCNSubtarget 574 return FMA; 1255 bool FMA; member in class:llvm::final 1340 bool hasFMA() const { return FMA; }
|
H A D | SIISelLowering.cpp | 596 setOperationAction(ISD::FMA, MVT::f16, Legal); 707 setOperationAction(ISD::FMA, MVT::v2f16, Legal); 734 setOperationAction(ISD::FMA, MVT::v4f16, Custom); 809 setTargetDAGCombine(ISD::FMA); 869 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && 4236 // free fneg'd operands. As long as we have fast FMA (controlled by 4444 case ISD::FMA: 8082 case ISD::FMA: 8227 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, 8230 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, S 10273 SDValue FMA = N->getOperand(2); local [all...] |
H A D | AMDGPUSubtarget.cpp | 545 FMA(false),
|
H A D | AMDGPUISelLowering.cpp | 482 setOperationAction(ISD::FMA, VT, Expand); 582 case ISD::FMA: 656 // Some users (such as 3-operand FMA/MAD) must use a VOP3 encoding, and thus 819 case ISD::FMA: 1703 (unsigned)ISD::FMA : 1790 (unsigned)ISD::FMA : 2584 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc); 3731 case ISD::FMA:
|
H A D | AMDGPUISelDAGToDAG.cpp | 877 case ISD::FMA: 2160 bool IsFMA = N->getOpcode() == ISD::FMA;
|
H A D | R600ISelLowering.cpp | 226 setOperationAction(ISD::FMA, MVT::f32, Expand); 227 setOperationAction(ISD::FMA, MVT::f64, Expand);
|
/freebsd-13-stable/sys/cddl/dev/dtrace/x86/ |
H A D | dis_tables.c | 244 FMA, /* FMA instructions, all VEX_RMrX */ enumerator in enum:__anon8768 1550 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1551 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1552 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,1 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 430 /// FMA - Perform a * b + c with no intermediate rounding step. 431 FMA, enumerator in enum:llvm::ISD::NodeType
|
H A D | BasicTTIImpl.h | 1366 ISDs.push_back(ISD::FMA); 1369 ISDs.push_back(ISD::FMA); 1616 // If we can't lower fmuladd into an FMA estimate the cost as a floating
|
/freebsd-13-stable/sys/xen/interface/arch-x86/ |
H A D | cpufeatureset.h | 135 XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | InterleavedLoadCombinePass.cpp | 1184 auto FMA = MSSA.getMemoryAccess(First); local 1187 if (!MSSA.dominates(MADef, FMA))
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/IR/ |
H A D | AutoUpgrade.cpp | 3177 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); local 3178 Rep = Builder.CreateCall(FMA, Ops); 3180 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), local 3183 Rep = Builder.CreateCall(FMA, { A, B, C }); 3237 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), local 3240 Rep = Builder.CreateCall(FMA, { A, B, C }); 3298 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, local 3300 Value *Odd = Builder.CreateCall(FMA, Ops); 3302 Value *Even = Builder.CreateCall(FMA, Ops);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 931 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), 932 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), 933 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND), 934 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 260 case ISD::FMA: return "fma";
|
H A D | DAGCombiner.cpp | 1651 case ISD::FMA: return visitFMA(N); 11973 /// Try to perform FMA combining on a given FADD node. 11988 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT)); 12007 // Always prefer FMAD to FMA for precision. 12008 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; 12041 SDValue FMA, E; local 12045 FMA = N0; 12050 FMA = N1; 12053 if (FMA && E) { 12054 SDValue A = FMA [all...] |
H A D | LegalizeFloatTypes.cpp | 95 case ISD::FMA: R = SoftenFloatRes_FMA(N); break; 1175 case ISD::FMA: ExpandFloatRes_FMA(N, Lo, Hi); break; 2180 case ISD::FMA: // FMA is same as FMAD 2521 case ISD::FMA: // FMA is same as FMAD
|
H A D | LegalizeVectorOps.cpp | 435 case ISD::FMA:
|
H A D | LegalizeVectorTypes.cpp | 149 case ISD::FMA: 944 case ISD::FMA: 2898 case ISD::FMA:
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetTransformInfo.cpp | 325 case Intrinsic::fma: Opcode = ISD::FMA; break;
|
H A D | PPCISelLowering.cpp | 334 setOperationAction(ISD::FMA , MVT::f64, Expand); 335 setOperationAction(ISD::FMA , MVT::f32, Expand); 337 setOperationAction(ISD::FMA , MVT::f64, Legal); 338 setOperationAction(ISD::FMA , MVT::f32, Legal); 800 setOperationAction(ISD::FMA, MVT::v4f32, Legal); 871 setOperationAction(ISD::FMA, MVT::v2f64, Legal); 1019 setOperationAction(ISD::FMA, MVT::f128, Legal); 1274 setTargetDAGCombine(ISD::FMA); 1594 assert(VT.isFloatingPoint() && "Non-floating-point FMA?"); 8590 Value = DAG.getNode(ISD::FMA, d [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1611 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, 1713 setOperationAction(ISD::FMA, MVT::f64, Expand); 2044 return isOperationLegalOrCustom(ISD::FMA, VT);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 137 setOperationAction(ISD::FMA, MVT::f16, Promote); 392 setOperationAction(ISD::FMA, Ty, Legal); 1902 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1627 setOperationAction(ISD::FMA , MVT::f128, Expand); 1632 setOperationAction(ISD::FMA , MVT::f64, Expand); 1637 setOperationAction(ISD::FMA , MVT::f32, Expand);
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 92 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA})
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 75 cl::desc("NVPTX Specific: FMA contraction (0: don't do it" 520 for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) { 4386 // which guarantees that the FMA will not increase register pressure at node N. 4418 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
|