1/* 2 * arch-x86/cpufeatureset.h 3 * 4 * CPU featureset definitions 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Copyright (c) 2015, 2016 Citrix Systems, Inc. 25 */ 26 27/* 28 * There are two expected ways of including this header. 29 * 30 * 1) The "default" case (expected from tools etc). 31 * 32 * Simply #include <public/arch-x86/cpufeatureset.h> 33 * 34 * In this circumstance, normal header guards apply and the includer shall get 35 * an enumeration in the XEN_X86_FEATURE_xxx namespace. 36 * 37 * 2) The special case where the includer provides XEN_CPUFEATURE() in scope. 38 * 39 * In this case, no inclusion guards apply and the caller is responsible for 40 * their XEN_CPUFEATURE() being appropriate in the included context. 41 */ 42 43#ifndef XEN_CPUFEATURE 44 45/* 46 * Includer has not provided a custom XEN_CPUFEATURE(). Arrange for normal 47 * header guards, an enum and constants in the XEN_X86_FEATURE_xxx namespace. 48 */ 49#ifndef __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ 50#define __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ 51 52#define XEN_CPUFEATURESET_DEFAULT_INCLUDE 53 54#define XEN_CPUFEATURE(name, value) XEN_X86_FEATURE_##name = value, 55enum { 56 57#endif /* __XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H__ */ 58#endif /* !XEN_CPUFEATURE */ 59 60 61#ifdef XEN_CPUFEATURE 62/* 63 * A featureset is a bitmap of x86 features, represented as a collection of 64 * 32bit words. 65 * 66 * Words are as specified in vendors programming manuals, and shall not 67 * contain any synthesied values. New words may be added to the end of 68 * featureset. 69 * 70 * All featureset words currently originate from leaves specified for the 71 * CPUID instruction, but this is not preclude other sources of information. 72 */ 73 74/* 75 * Attribute syntax: 76 * 77 * Attributes for a particular feature are provided as characters before the 78 * first space in the comment immediately following the feature value. Note - 79 * none of these attributes form part of the Xen public ABI. 80 * 81 * Special: '!' 82 * This bit has special properties and is not a straight indication of a 83 * piece of new functionality. Xen will handle these differently, 84 * and may override toolstack settings completely. 85 * 86 * Applicability to guests: 'A', 'S' or 'H' 87 * 'A' = All guests. 88 * 'S' = All HVM guests (not PV guests). 89 * 'H' = HVM HAP guests (not PV or HVM Shadow guests). 90 * Upper case => Available by default 91 * Lower case => Can be opted-in to, but not available by default. 92 */ 93 94/* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */ 95XEN_CPUFEATURE(FPU, 0*32+ 0) /*A Onboard FPU */ 96XEN_CPUFEATURE(VME, 0*32+ 1) /*S Virtual Mode Extensions */ 97XEN_CPUFEATURE(DE, 0*32+ 2) /*A Debugging Extensions */ 98XEN_CPUFEATURE(PSE, 0*32+ 3) /*S Page Size Extensions */ 99XEN_CPUFEATURE(TSC, 0*32+ 4) /*A Time Stamp Counter */ 100XEN_CPUFEATURE(MSR, 0*32+ 5) /*A Model-Specific Registers, RDMSR, WRMSR */ 101XEN_CPUFEATURE(PAE, 0*32+ 6) /*A Physical Address Extensions */ 102XEN_CPUFEATURE(MCE, 0*32+ 7) /*A Machine Check Architecture */ 103XEN_CPUFEATURE(CX8, 0*32+ 8) /*A CMPXCHG8 instruction */ 104XEN_CPUFEATURE(APIC, 0*32+ 9) /*!A Onboard APIC */ 105XEN_CPUFEATURE(SEP, 0*32+11) /*A SYSENTER/SYSEXIT */ 106XEN_CPUFEATURE(MTRR, 0*32+12) /*S Memory Type Range Registers */ 107XEN_CPUFEATURE(PGE, 0*32+13) /*S Page Global Enable */ 108XEN_CPUFEATURE(MCA, 0*32+14) /*A Machine Check Architecture */ 109XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present) */ 110XEN_CPUFEATURE(PAT, 0*32+16) /*A Page Attribute Table */ 111XEN_CPUFEATURE(PSE36, 0*32+17) /*S 36-bit PSEs */ 112XEN_CPUFEATURE(CLFLUSH, 0*32+19) /*A CLFLUSH instruction */ 113XEN_CPUFEATURE(DS, 0*32+21) /* Debug Store */ 114XEN_CPUFEATURE(ACPI, 0*32+22) /*A ACPI via MSR */ 115XEN_CPUFEATURE(MMX, 0*32+23) /*A Multimedia Extensions */ 116XEN_CPUFEATURE(FXSR, 0*32+24) /*A FXSAVE and FXRSTOR instructions */ 117XEN_CPUFEATURE(SSE, 0*32+25) /*A Streaming SIMD Extensions */ 118XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */ 119XEN_CPUFEATURE(SS, 0*32+27) /*A CPU self snoop */ 120XEN_CPUFEATURE(HTT, 0*32+28) /*!A Hyper-Threading Technology */ 121XEN_CPUFEATURE(TM1, 0*32+29) /* Thermal Monitor 1 */ 122XEN_CPUFEATURE(PBE, 0*32+31) /* Pending Break Enable */ 123 124/* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */ 125XEN_CPUFEATURE(SSE3, 1*32+ 0) /*A Streaming SIMD Extensions-3 */ 126XEN_CPUFEATURE(PCLMULQDQ, 1*32+ 1) /*A Carry-less multiplication */ 127XEN_CPUFEATURE(DTES64, 1*32+ 2) /* 64-bit Debug Store */ 128XEN_CPUFEATURE(MONITOR, 1*32+ 3) /* Monitor/Mwait support */ 129XEN_CPUFEATURE(DSCPL, 1*32+ 4) /* CPL Qualified Debug Store */ 130XEN_CPUFEATURE(VMX, 1*32+ 5) /*S Virtual Machine Extensions */ 131XEN_CPUFEATURE(SMX, 1*32+ 6) /* Safer Mode Extensions */ 132XEN_CPUFEATURE(EIST, 1*32+ 7) /* Enhanced SpeedStep */ 133XEN_CPUFEATURE(TM2, 1*32+ 8) /* Thermal Monitor 2 */ 134XEN_CPUFEATURE(SSSE3, 1*32+ 9) /*A Supplemental Streaming SIMD Extensions-3 */ 135XEN_CPUFEATURE(FMA, 1*32+12) /*A Fused Multiply Add */ 136XEN_CPUFEATURE(CX16, 1*32+13) /*A CMPXCHG16B */ 137XEN_CPUFEATURE(XTPR, 1*32+14) /* Send Task Priority Messages */ 138XEN_CPUFEATURE(PDCM, 1*32+15) /* Perf/Debug Capability MSR */ 139XEN_CPUFEATURE(PCID, 1*32+17) /*H Process Context ID */ 140XEN_CPUFEATURE(DCA, 1*32+18) /* Direct Cache Access */ 141XEN_CPUFEATURE(SSE4_1, 1*32+19) /*A Streaming SIMD Extensions 4.1 */ 142XEN_CPUFEATURE(SSE4_2, 1*32+20) /*A Streaming SIMD Extensions 4.2 */ 143XEN_CPUFEATURE(X2APIC, 1*32+21) /*!A Extended xAPIC */ 144XEN_CPUFEATURE(MOVBE, 1*32+22) /*A movbe instruction */ 145XEN_CPUFEATURE(POPCNT, 1*32+23) /*A POPCNT instruction */ 146XEN_CPUFEATURE(TSC_DEADLINE, 1*32+24) /*S TSC Deadline Timer */ 147XEN_CPUFEATURE(AESNI, 1*32+25) /*A AES instructions */ 148XEN_CPUFEATURE(XSAVE, 1*32+26) /*A XSAVE/XRSTOR/XSETBV/XGETBV */ 149XEN_CPUFEATURE(OSXSAVE, 1*32+27) /*! OSXSAVE */ 150XEN_CPUFEATURE(AVX, 1*32+28) /*A Advanced Vector Extensions */ 151XEN_CPUFEATURE(F16C, 1*32+29) /*A Half-precision convert instruction */ 152XEN_CPUFEATURE(RDRAND, 1*32+30) /*!A Digital Random Number Generator */ 153XEN_CPUFEATURE(HYPERVISOR, 1*32+31) /*!A Running under some hypervisor */ 154 155/* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */ 156XEN_CPUFEATURE(SYSCALL, 2*32+11) /*A SYSCALL/SYSRET */ 157XEN_CPUFEATURE(NX, 2*32+20) /*A Execute Disable */ 158XEN_CPUFEATURE(MMXEXT, 2*32+22) /*A AMD MMX extensions */ 159XEN_CPUFEATURE(FFXSR, 2*32+25) /*A FFXSR instruction optimizations */ 160XEN_CPUFEATURE(PAGE1GB, 2*32+26) /*H 1Gb large page support */ 161XEN_CPUFEATURE(RDTSCP, 2*32+27) /*A RDTSCP */ 162XEN_CPUFEATURE(LM, 2*32+29) /*A Long Mode (x86-64) */ 163XEN_CPUFEATURE(3DNOWEXT, 2*32+30) /*A AMD 3DNow! extensions */ 164XEN_CPUFEATURE(3DNOW, 2*32+31) /*A 3DNow! */ 165 166/* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */ 167XEN_CPUFEATURE(LAHF_LM, 3*32+ 0) /*A LAHF/SAHF in long mode */ 168XEN_CPUFEATURE(CMP_LEGACY, 3*32+ 1) /*!A If yes HyperThreading not valid */ 169XEN_CPUFEATURE(SVM, 3*32+ 2) /*S Secure virtual machine */ 170XEN_CPUFEATURE(EXTAPIC, 3*32+ 3) /* Extended APIC space */ 171XEN_CPUFEATURE(CR8_LEGACY, 3*32+ 4) /*S CR8 in 32-bit mode */ 172XEN_CPUFEATURE(ABM, 3*32+ 5) /*A Advanced bit manipulation */ 173XEN_CPUFEATURE(SSE4A, 3*32+ 6) /*A SSE-4A */ 174XEN_CPUFEATURE(MISALIGNSSE, 3*32+ 7) /*A Misaligned SSE mode */ 175XEN_CPUFEATURE(3DNOWPREFETCH, 3*32+ 8) /*A 3DNow prefetch instructions */ 176XEN_CPUFEATURE(OSVW, 3*32+ 9) /* OS Visible Workaround */ 177XEN_CPUFEATURE(IBS, 3*32+10) /* Instruction Based Sampling */ 178XEN_CPUFEATURE(XOP, 3*32+11) /*A extended AVX instructions */ 179XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ 180XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ 181XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ 182XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ 183XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ 184XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ 185XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ 186XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ 187XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MWAITX) */ 188 189/* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ 190XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) /*A XSAVEOPT instruction */ 191XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ 192XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ 193XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ 194 195/* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ 196XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ 197XEN_CPUFEATURE(TSC_ADJUST, 5*32+ 1) /*S TSC_ADJUST MSR available */ 198XEN_CPUFEATURE(SGX, 5*32+ 2) /* Software Guard extensions */ 199XEN_CPUFEATURE(BMI1, 5*32+ 3) /*A 1st bit manipulation extensions */ 200XEN_CPUFEATURE(HLE, 5*32+ 4) /*A Hardware Lock Elision */ 201XEN_CPUFEATURE(AVX2, 5*32+ 5) /*A AVX2 instructions */ 202XEN_CPUFEATURE(FDP_EXCP_ONLY, 5*32+ 6) /*! x87 FDP only updated on exception. */ 203XEN_CPUFEATURE(SMEP, 5*32+ 7) /*S Supervisor Mode Execution Protection */ 204XEN_CPUFEATURE(BMI2, 5*32+ 8) /*A 2nd bit manipulation extensions */ 205XEN_CPUFEATURE(ERMS, 5*32+ 9) /*A Enhanced REP MOVSB/STOSB */ 206XEN_CPUFEATURE(INVPCID, 5*32+10) /*H Invalidate Process Context ID */ 207XEN_CPUFEATURE(RTM, 5*32+11) /*A Restricted Transactional Memory */ 208XEN_CPUFEATURE(PQM, 5*32+12) /* Platform QoS Monitoring */ 209XEN_CPUFEATURE(NO_FPU_SEL, 5*32+13) /*! FPU CS/DS stored as zero */ 210XEN_CPUFEATURE(MPX, 5*32+14) /*s Memory Protection Extensions */ 211XEN_CPUFEATURE(PQE, 5*32+15) /* Platform QoS Enforcement */ 212XEN_CPUFEATURE(AVX512F, 5*32+16) /*A AVX-512 Foundation Instructions */ 213XEN_CPUFEATURE(AVX512DQ, 5*32+17) /*A AVX-512 Doubleword & Quadword Instrs */ 214XEN_CPUFEATURE(RDSEED, 5*32+18) /*A RDSEED instruction */ 215XEN_CPUFEATURE(ADX, 5*32+19) /*A ADCX, ADOX instructions */ 216XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode Access Prevention */ 217XEN_CPUFEATURE(AVX512_IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add */ 218XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */ 219XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */ 220XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */ 221XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal Instrs */ 222XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs */ 223XEN_CPUFEATURE(SHA, 5*32+29) /*A SHA1 & SHA256 instructions */ 224XEN_CPUFEATURE(AVX512BW, 5*32+30) /*A AVX-512 Byte and Word Instructions */ 225XEN_CPUFEATURE(AVX512VL, 5*32+31) /*A AVX-512 Vector Length Extensions */ 226 227/* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */ 228XEN_CPUFEATURE(PREFETCHWT1, 6*32+ 0) /*A PREFETCHWT1 instruction */ 229XEN_CPUFEATURE(AVX512_VBMI, 6*32+ 1) /*A AVX-512 Vector Byte Manipulation Instrs */ 230XEN_CPUFEATURE(UMIP, 6*32+ 2) /*S User Mode Instruction Prevention */ 231XEN_CPUFEATURE(PKU, 6*32+ 3) /*H Protection Keys for Userspace */ 232XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*! OS Protection Keys Enable */ 233XEN_CPUFEATURE(AVX512_VBMI2, 6*32+ 6) /*A Additional AVX-512 Vector Byte Manipulation Instrs */ 234XEN_CPUFEATURE(CET_SS, 6*32+ 7) /* CET - Shadow Stacks */ 235XEN_CPUFEATURE(GFNI, 6*32+ 8) /*A Galois Field Instrs */ 236XEN_CPUFEATURE(VAES, 6*32+ 9) /*A Vector AES Instrs */ 237XEN_CPUFEATURE(VPCLMULQDQ, 6*32+10) /*A Vector Carry-less Multiplication Instrs */ 238XEN_CPUFEATURE(AVX512_VNNI, 6*32+11) /*A Vector Neural Network Instrs */ 239XEN_CPUFEATURE(AVX512_BITALG, 6*32+12) /*A Support for VPOPCNT[B,W] and VPSHUFBITQMB */ 240XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A POPCNT for vectors of DW/QW */ 241XEN_CPUFEATURE(TSXLDTRK, 6*32+16) /*a TSX load tracking suspend/resume insns */ 242XEN_CPUFEATURE(RDPID, 6*32+22) /*A RDPID instruction */ 243XEN_CPUFEATURE(CLDEMOTE, 6*32+25) /*A CLDEMOTE instruction */ 244XEN_CPUFEATURE(MOVDIRI, 6*32+27) /*a MOVDIRI instruction */ 245XEN_CPUFEATURE(MOVDIR64B, 6*32+28) /*a MOVDIR64B instruction */ 246XEN_CPUFEATURE(ENQCMD, 6*32+29) /* ENQCMD{,S} instructions */ 247 248/* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */ 249XEN_CPUFEATURE(ITSC, 7*32+ 8) /* Invariant TSC */ 250XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ 251 252/* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ 253XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ 254XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ 255XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ 256XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ 257XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ 258 259/* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ 260XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ 261XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ 262XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */ 263XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */ 264XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ 265XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ 266XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ 267XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ 268XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ 269XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ 270XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /*a IA32_ARCH_CAPABILITIES MSR */ 271XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ 272XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ 273 274/* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */ 275XEN_CPUFEATURE(AVX512_BF16, 10*32+ 5) /*A AVX512 BFloat16 Instructions */ 276 277#endif /* XEN_CPUFEATURE */ 278 279/* Clean up from a default include. Close the enum (for C). */ 280#ifdef XEN_CPUFEATURESET_DEFAULT_INCLUDE 281#undef XEN_CPUFEATURESET_DEFAULT_INCLUDE 282#undef XEN_CPUFEATURE 283}; 284 285#endif /* XEN_CPUFEATURESET_DEFAULT_INCLUDE */ 286 287/* 288 * Local variables: 289 * mode: C 290 * c-file-style: "BSD" 291 * c-basic-offset: 4 292 * tab-width: 4 293 * indent-tabs-mode: nil 294 * End: 295 */ 296