Searched refs:CTLZ (Results 1 - 25 of 32) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2255 // CTLZ: llvm\test\CodeGen\X86\vector-lzcnt-*.ll
2259 { ISD::CTLZ, MVT::v8i64, 1 },
2260 { ISD::CTLZ, MVT::v16i32, 1 },
2261 { ISD::CTLZ, MVT::v32i16, 8 },
2262 { ISD::CTLZ, MVT::v64i8, 20 },
2263 { ISD::CTLZ, MVT::v4i64, 1 },
2264 { ISD::CTLZ, MVT::v8i32, 1 },
2265 { ISD::CTLZ, MVT::v16i16, 4 },
2266 { ISD::CTLZ, MVT::v32i8, 10 },
2267 { ISD::CTLZ, MV
[all...]
H A DX86ISelLowering.cpp353 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
359 setOperationAction(ISD::CTLZ , VT, Custom);
797 setOperationAction(ISD::CTLZ, VT, Expand);
1060 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1061 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1062 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1063 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1258 setOperationAction(ISD::CTLZ, VT, Custom);
1618 setOperationAction(ISD::CTLZ, VT, Custom);
1645 setOperationAction(ISD::CTLZ, V
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp182 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, local
254 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True});
255 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True});
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h587 CTLZ, enumerator in enum:llvm::ISD::NodeType
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp392 case ISD::CTLZ:
774 case ISD::CTLZ:
H A DSelectionDAGDumper.cpp411 case ISD::CTLZ: return "ctlz";
H A DTargetLowering.cpp3390 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
6610 isOperationLegalOrCustom(ISD::CTLZ, VT)) {
6611 Result = DAG.getNode(ISD::CTLZ, dl, VT, Op);
6619 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
6623 DAG.getConstant(NumBitsPerElt, dl, VT), CTLZ);
6682 !isOperationLegalOrCustom(ISD::CTLZ, VT)) ||
6696 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6697 if (isOperationLegal(ISD::CTLZ, VT) && !isOperationLegal(ISD::CTPOP, VT)) {
6700 DAG.getNode(ISD::CTLZ, dl, VT, Tmp));
7300 SDValue Clz = DAG.getNode(ISD::CTLZ, d
[all...]
H A DLegalizeVectorTypes.cpp76 case ISD::CTLZ:
869 case ISD::CTLZ:
2014 case ISD::CTLZ:
2888 case ISD::CTLZ:
H A DLegalizeDAG.cpp2791 case ISD::CTLZ:
4334 case ISD::CTLZ:
4356 if (Node->getOpcode() == ISD::CTLZ ||
H A DLegalizeIntegerTypes.cpp64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
1927 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
H A DDAGCombiner.cpp1626 case ISD::CTLZ: return visitCTLZ(N);
8396 if (N1C && N0.getOpcode() == ISD::CTLZ &&
8412 // could be set on input to the CTLZ node. If this bit is set, the SRL
8413 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
8651 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
21415 if ((Count.getOpcode() == ISD::CTLZ ||
21418 (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
21419 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
21502 SDValue Ctlz = DAG.getNode(ISD::CTLZ, DL, VT, V);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp113 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp91 setOperationAction(ISD::CTLZ, T, Legal);
153 setOperationAction(ISD::CTLZ, T, Custom);
1339 // Lower vector CTTZ into a computation using CTLZ (Hacker's Delight):
1369 {VecW, DAG.getNode(ISD::CTLZ, dl, ResTy, A)});
1708 case ISD::CTLZ:
H A DHexagonISelLowering.cpp1536 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1537 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1609 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp107 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
108 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp629 setOperationAction(ISD::CTLZ, IntVT, Legal);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp382 setOperationAction(ISD::CTLZ, VT, Expand);
415 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
455 setOperationAction(ISD::CTLZ, VT, Expand);
1255 case ISD::CTLZ:
2300 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp127 setOperationAction(ISD::CTLZ, MVT::i32, Legal);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp275 setOperationAction(ISD::CTLZ, VT, Legal);
919 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
920 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
1148 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
3877 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3897 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3904 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
6166 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB); local
6167 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp184 setOperationAction(ISD::CTLZ, VT, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp166 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp335 setOperationAction(ISD::CTLZ, Ty, Legal);
2084 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
H A DMipsISelLowering.cpp481 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
483 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1575 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1639 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp162 setOperationAction(ISD::CTLZ, XLenVT, Expand);

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