| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineMulDivRem.cpp | 507 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
508 if (CC1->isNormalFP())
509 return BinaryOperator::CreateFDivFMF(CC1, X, &I);
529 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
531 return BinaryOperator::CreateFAddFMF(XC, CC1, &I);
535 Constant *CC1 = ConstantExpr::getFMul(C, C1); local
537 return BinaryOperator::CreateFSubFMF(CC1, XC, &I);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 1680 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1687 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1691 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1710 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1729 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1730 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
1733 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1734 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
|
| H A D | DAGCombiner.cpp | 4644 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get(); local
4646 if (LR == RR && CC0 == CC1 && IsInteger) {
4651 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4653 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4655 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4657 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4666 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4670 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4672 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4674 bool OrNeNeg1 = !IsAnd && CC1
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5482 AArch64CC::CondCode CC1, CC2; local
5483 changeFPCCToAArch64CC(CC, CC1, CC2);
5484 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5696 AArch64CC::CondCode CC1, CC2; local
5697 changeFPCCToAArch64CC(CC, CC1, CC2);
5700 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, LHS.getValueType()), CC1, local
5702 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5715 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
5877 AArch64CC::CondCode CC1, CC2; local
5878 changeFPCCToAArch64CC(CC, CC1, CC
9151 AArch64CC::CondCode CC1, CC2; local
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2794 AArch64CC::CondCode CC1, CC2;
2796 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
2819 .addImm(getInvertedCondCode(CC1));
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 550 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
552 if (CC1 == CC2)
555 switch (CC1) {
|
| H A D | ARMISelLowering.cpp | 5026 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get(); local
5067 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
5073 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22296 unsigned CC0, CC1;
22300 CC1 = 0; // EQ
22305 CC1 = 4; // NEQ
22316 {Chain, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8)});
22323 Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8));
[all...] |