/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCCallingConv.cpp | 36 static const MCPhysReg ArgRegs[] = { local 40 const unsigned NumArgRegs = array_lengthof(ArgRegs); 42 unsigned RegNum = State.getFirstUnallocated(ArgRegs); 46 // allocated yet. RegNum is actually an index into ArgRegs, which means we 49 State.AllocateReg(ArgRegs[RegNum]); 61 static const MCPhysReg ArgRegs[] = { local 65 const unsigned NumArgRegs = array_lengthof(ArgRegs); 67 unsigned RegNum = State.getFirstUnallocated(ArgRegs); 74 State.AllocateReg(ArgRegs[RegNum + i]); 86 static const MCPhysReg ArgRegs[] local [all...] |
H A D | PPCFastISel.cpp | 190 SmallVectorImpl<unsigned> &ArgRegs, 1378 SmallVectorImpl<unsigned> &ArgRegs, 1435 unsigned Arg = ArgRegs[VA.getValNo()]; 1602 SmallVector<unsigned, 8> ArgRegs; local 1607 ArgRegs.reserve(NumArgs); 1633 ArgRegs.push_back(Arg); 1642 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 1377 processCallArgs(SmallVectorImpl<Value*> &Args, SmallVectorImpl<unsigned> &ArgRegs, SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, SmallVectorImpl<unsigned> &RegArgs, CallingConv::ID CC, unsigned &NumBytes, bool IsVarArg) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 463 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); local 464 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); 468 if (ArgRegs.size() == Idx) 473 (int)(RegSize * (ArgRegs.size() - Idx)); 480 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { 481 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); 484 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
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H A D | MipsISelLowering.cpp | 4398 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); local 4409 unsigned ArgReg = ArgRegs[FirstReg + I]; 4458 unsigned ArgReg = ArgRegs[FirstReg + I]; 4481 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); local 4482 unsigned Idx = State.getFirstUnallocated(ArgRegs); 4493 if (ArgRegs.size() == Idx) 4498 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); 4510 for (unsigned I = Idx; I < ArgRegs.size(); 4512 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 521 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, local 524 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); 525 if (FirstVAReg < array_lengthof(ArgRegs)) { 529 // There are (array_lengthof(ArgRegs) - FirstVAReg) registers which 532 MFI.CreateFixedObject((array_lengthof(ArgRegs) - FirstVAReg) * 4, 536 for (unsigned i = FirstVAReg; i < array_lengthof(ArgRegs); i++) { 539 RegInfo.addLiveIn(ArgRegs[i], VReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | CallLowering.h | 330 /// \p ArgRegs is a list of lists of virtual registers containing each 332 /// ArgRegs[i]). For each argument, there will be one register for each 347 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | CallLowering.cpp | 35 ArrayRef<ArrayRef<Register>> ArgRegs, 47 ArgInfo OrigArg{ArgRegs[i], Arg->getType(), ISD::ArgFlagsTy{}, 33 lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB, ArrayRef<Register> ResRegs, ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg, std::function<unsigned()> GetCalleeReg) const argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 221 SmallVectorImpl<Register> &ArgRegs, 1875 SmallVectorImpl<Register> &ArgRegs, 1942 Register Arg = ArgRegs[VA.getValNo()]; 2223 SmallVector<Register, 8> ArgRegs; local 2227 ArgRegs.reserve(I->getNumOperands()); 2242 ArgRegs.push_back(Arg); 2250 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 2330 SmallVector<Register, 8> ArgRegs; local 2335 ArgRegs.reserve(arg_size); 2373 ArgRegs 1874 ProcessCallArgs(SmallVectorImpl<Value*> &Args, SmallVectorImpl<Register> &ArgRegs, SmallVectorImpl<MVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, SmallVectorImpl<Register> &RegArgs, CallingConv::ID CC, unsigned &NumBytes, bool isVarArg) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1347 static const MCPhysReg ArgRegs[] = { local 1351 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); 1352 if (FirstVAReg < array_lengthof(ArgRegs)) { 1356 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { 1366 RegInfo.addLiveIn(ArgRegs[i], VReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2042 ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs); local 2043 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); 2056 if (ArgRegs.size() == Idx) { 2060 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); 2079 for (unsigned I = Idx; I < ArgRegs.size(); 2082 RegInfo.addLiveIn(ArgRegs[I], Reg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 140 static const MCPhysReg ArgRegs[] = { local 144 const unsigned NumArgRegs = array_lengthof(ArgRegs); 145 unsigned RegNum = State.getFirstUnallocated(ArgRegs); 147 // RegNum is an index into ArgRegs: skip a register if RegNum is odd. 149 State.AllocateReg(ArgRegs[RegNum]);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 532 // Store remaining ArgRegs to the stack if this is a varargs function. 534 static const MCPhysReg ArgRegs[] = { local 537 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); 538 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3245 SmallVector<unsigned, 16> ArgRegs; local 3290 ArgRegs.push_back(ResultReg); 3322 unsigned ArgReg = ArgRegs[VA.getValNo()];
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