| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | Allocator.h | 179 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); local
180 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize);
181 char *AlignedPtr = (char*)AlignedAddr;
189 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); local
190 assert(AlignedAddr + SizeToAllocate <= (uintptr_t)End &&
192 char *AlignedPtr = (char*)AlignedAddr;
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 194 Value *AlignedAddr, Value *Incr,
201 Value *AlignedAddr, Value *CmpVal,
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| H A D | RISCVISelLowering.cpp | 2904 IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
2909 Type *Tys[] = {AlignedAddr->getType()};
2935 {AlignedAddr, Incr, Mask, SextShamt, Ordering});
2938 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering});
2956 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
2967 Type *Tys[] = {AlignedAddr->getType()};
2971 MaskedCmpXchg, {AlignedAddr, CmpVal, NewVal, Mask, Ordering});
2903 emitMaskedAtomicRMWIntrinsic( IRBuilder< &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const argument
2955 emitMaskedAtomicCmpXchgIntrinsic( IRBuilder< &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | AtomicExpandPass.cpp | 583 Value *AlignedAddr = nullptr; member in struct:__anon3438::PartwordMaskValues
604 O << " AlignedAddr: ";
605 PrintObj(PMV.AlignedAddr);
624 /// AlignedAddr: Addr rounded down to a multiple of WordSize
648 PMV.AlignedAddr = Addr;
658 PMV.AlignedAddr = Builder.CreateIntToPtr(
660 "AlignedAddr");
782 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder,
786 OldResult = insertRMWLLSCLoop(Builder, PMV.WordType, PMV.AlignedAddr,
820 AtomicRMWInst *NewAI = Builder.CreateAtomicRMW(Op, PMV.AlignedAddr,
[all...] |
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 1673 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); local
1792 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1819 .addReg(AlignedAddr)
1922 Register AlignedAddr = RegInfo.createVirtualRegister(RCp); local
1979 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
2011 .addReg(AlignedAddr)
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1847 Value *AlignedAddr, Value *Incr,
1857 IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1845 emitMaskedAtomicRMWIntrinsic(IRBuilder< &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const argument
1856 emitMaskedAtomicCmpXchgIntrinsic( IRBuilder< &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3899 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, local
3928 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
4015 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, local
4031 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
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