Searched refs:__BIT (Results 1 - 17 of 17) sorted by relevance
/freebsd-12-stable/sys/dev/qat/ |
H A D | qat_c62xreg.h | 79 #define SOFTSTRAP_SS_POWERGATE_CY_C62X __BIT(23) 80 #define SOFTSTRAP_SS_POWERGATE_PKE_C62X __BIT(24) 94 #define ENABLE_AE_ECC_ERR_C62X __BIT(28) 95 #define ENABLE_AE_ECC_PARITY_CORR_C62X (__BIT(24) | __BIT(12)) 96 #define ERRSSMSH_EN_C62X __BIT(3) 98 #define PPERR_EN_C62X (__BIT(2)) 106 #define ERRMSK0_CERR_C62X (__BIT(24) | __BIT(16) | __BIT( [all...] |
H A D | qat_d15xxreg.h | 79 #define SOFTSTRAP_SS_POWERGATE_CY_D15XX __BIT(23) 80 #define SOFTSTRAP_SS_POWERGATE_PKE_D15XX __BIT(24) 94 #define ENABLE_AE_ECC_ERR_D15XX __BIT(28) 95 #define ENABLE_AE_ECC_PARITY_CORR_D15XX (__BIT(24) | __BIT(12)) 96 #define ERRSSMSH_EN_D15XX __BIT(3) 98 #define PPERR_EN_D15XX (__BIT(2)) 106 #define ERRMSK0_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT( [all...] |
H A D | qat_c3xxxreg.h | 79 #define SOFTSTRAP_SS_POWERGATE_CY_C3XXX __BIT(23) 80 #define SOFTSTRAP_SS_POWERGATE_PKE_C3XXX __BIT(24) 94 #define ENABLE_AE_ECC_ERR_C3XXX __BIT(28) 95 #define ENABLE_AE_ECC_PARITY_CORR_C3XXX (__BIT(24) | __BIT(12)) 96 #define ERRSSMSH_EN_C3XXX __BIT(3) 98 #define PPERR_EN_C3XXX (__BIT(2)) 106 #define ERRMSK0_CERR_C3XXX (__BIT(24) | __BIT(16) | __BIT( [all...] |
H A D | qat_dh895xccreg.h | 98 #define ENABLE_AE_ECC_ERR_DH895XCC __BIT(28) 99 #define ENABLE_AE_ECC_PARITY_CORR_DH895XCC (__BIT(24) | __BIT(12)) 100 #define ERRSSMSH_EN_DH895XCC __BIT(3) 102 #define PPERR_EN_DH895XCC (__BIT(2))
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H A D | qat_hw15reg.h | 76 #define ARCH_IF_FLAGS_VALID_FLAG __BIT(7) 408 #define COMN_RESP_CRYPTO_STATUS __BIT(7) 409 #define COMN_RESP_PKE_STATUS __BIT(6) 410 #define COMN_RESP_CMP_STATUS __BIT(5) 411 #define COMN_RESP_XLAT_STATUS __BIT(4) 412 #define COMN_RESP_PM_STATUS __BIT(3) 413 #define COMN_RESP_INIT_ADMIN_STATUS __BIT(2) 537 #define LA_FLAGS_GCM_IV_LEN_FLAG __BIT(9) 543 #define LA_FLAGS_DIGEST_IN_BUFFER __BIT(5) 544 #define LA_FLAGS_CMP_AUTH_RES __BIT( [all...] |
H A D | qatreg.h | 65 #define __BIT(__n) \ macro 69 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) 113 #define FUSECTL_MASK __BIT(31) 116 #define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0) 117 #define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1) 118 #define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2) 119 #define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3) 120 #define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4) 121 #define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT( [all...] |
H A D | qat_hw17reg.h | 559 #define FW_COMN_VALID __BIT(7) 1219 #define FW_LA_ZUC_3G_PROTO __BIT(12) 1223 #define FW_LA_GCM_IV_LEN_12_OCTETS __BIT(11) 1227 #define FW_LA_DIGEST_IN_BUFFER __BIT(10) 1232 #define FW_LA_PROTO_SNOW_3G __BIT(9) 1234 #define FW_LA_PROTO_GCM __BIT(8) 1236 #define FW_LA_PROTO_CCM __BIT(7) 1241 #define FW_LA_CMP_AUTH_RES __BIT(6) 1245 #define FW_LA_RET_AUTH_RES __BIT(5) 1249 #define FW_LA_UPDATE_STATE __BIT( [all...] |
/freebsd-12-stable/sys/dev/bwi/ |
H A D | if_bwireg.h | 50 #define BWI_IMSTATE_INBAND_ERR __BIT(17) 51 #define BWI_IMSTATE_TIMEOUT __BIT(18) 56 #define BWI_STATE_LO_RESET __BIT(0) 57 #define BWI_STATE_LO_DISABLE1 __BIT(1) 58 #define BWI_STATE_LO_DISABLE2 __BIT(2) 59 #define BWI_STATE_LO_CLOCK __BIT(16) 60 #define BWI_STATE_LO_GATED_CLOCK __BIT(17) 61 #define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0) 62 #define BWI_STATE_LO_FLAG_PHYRST __BIT(1) 63 #define BWI_STATE_LO_FLAG_PHYLNK __BIT(1 [all...] |
H A D | bitops.h | 41 * __BIT(n): Return a bitmask with bit m set, where the least 69 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 70 #define __BIT(__n) (((__n) == 32) ? 0 : ((uint32_t)1 << (__n))) macro 74 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
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H A D | if_bwivar.h | 135 #define BWI_DESC32_C_EOR __BIT(28) 136 #define BWI_DESC32_C_INTR __BIT(29) 137 #define BWI_DESC32_C_FRAME_END __BIT(30) 138 #define BWI_DESC32_C_FRAME_START __BIT(31) 162 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14) 163 #define BWI_RXH_F1_SHPREAMBLE __BIT(7) 164 #define BWI_RXH_F1_OFDM __BIT(0) 166 #define BWI_RXH_F2_TYPE2FRAME __BIT(2) 168 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10) 200 #define BWI_TXH_PHY_C_OFDM __BIT( [all...] |
H A D | bwirf.h | 129 #define BWI_RFR_BBP_ATTEN_CALIB_BIT __BIT(0)
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/freebsd-12-stable/sys/mips/atheros/ar531x/ |
H A D | ar5312reg.h | 74 #define AR5312_FLASHCTL_RBLE __BIT(10) /* rd byte enable */ 85 #define AR5312_FLASHCTL_E __BIT(19) /* enable */ 86 #define AR5312_FLASHCTL_BUSERR __BIT(24) /* buserr */ 87 #define AR5312_FLASHCTL_WPERR __BIT(25) /* wperr */ 88 #define AR5312_FLASHCTL_WP __BIT(26) /* wp */ 89 #define AR5312_FLASHCTL_BM __BIT(27) /* bm */ 127 #define AR5312_RESET_SYSTEM __BIT(0) 128 #define AR5312_RESET_CPU __BIT(1) 129 #define AR5312_RESET_WLAN0 __BIT(2) /* mac & bb */ 130 #define AR5312_RESET_PHY0 __BIT( [all...] |
H A D | ar5315reg.h | 231 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 232 #define __BIT(__n) \ macro 237 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
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/freebsd-12-stable/lib/libnetbsd/sys/ |
H A D | cdefs.h | 76 /* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 77 #define __BIT(__n) \ macro 83 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))
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/freebsd-12-stable/contrib/netbsd-tests/include/ |
H A D | t_paths.c | 46 #define PATH_DEV __BIT(0) /* A device node */ 47 #define PATH_DIR __BIT(1) /* A directory */ 48 #define PATH_FILE __BIT(2) /* A file */ 49 #define PATH_ROOT __BIT(3) /* Access for root only */ 50 #define PATH_OPT __BIT(3) /* Optional, ENODEV if not supported */
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/freebsd-12-stable/contrib/netbsd-tests/lib/libc/sys/ |
H A D | t_wait_noproc.c | 161 if (pos & __BIT(n)) 210 if (pos & __BIT(n))
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/freebsd-12-stable/sys/arm/freescale/imx/ |
H A D | imx51_ipuv3reg.h | 159 #define CM_GPR_IPU_GP(n) __BIT((n)) 634 #define DMFC_STAT_FIFO_EMPTY(n) __BIT(12 + (n)) 635 #define DMFC_STAT_FIFO_FULL(n) __BIT((n))
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