1/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */ 2/* $NetBSD: qat_d15xxreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 3 4/* 5 * Copyright (c) 2019 Internet Initiative Japan, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Copyright(c) 2014 Intel Corporation. 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name of Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59/* $FreeBSD$ */ 60 61#ifndef _DEV_PCI_QAT_D15XXREG_H_ 62#define _DEV_PCI_QAT_D15XXREG_H_ 63 64/* Max number of accelerators and engines */ 65#define MAX_ACCEL_D15XX 5 66#define MAX_AE_D15XX 10 67 68/* PCIe BAR index */ 69#define BAR_SRAM_ID_D15XX 0 70#define BAR_PMISC_ID_D15XX 1 71#define BAR_ETR_ID_D15XX 2 72 73/* BAR PMISC sub-regions */ 74#define AE_OFFSET_D15XX 0x20000 75#define AE_LOCAL_OFFSET_D15XX 0x20800 76#define CAP_GLOBAL_OFFSET_D15XX 0x30000 77 78#define SOFTSTRAP_REG_D15XX 0x2EC 79#define SOFTSTRAP_SS_POWERGATE_CY_D15XX __BIT(23) 80#define SOFTSTRAP_SS_POWERGATE_PKE_D15XX __BIT(24) 81 82#define ACCEL_REG_OFFSET_D15XX 16 83#define ACCEL_MASK_D15XX 0x1F 84#define AE_MASK_D15XX 0x3FF 85 86#define SMIAPF0_D15XX 0x3A028 87#define SMIAPF1_D15XX 0x3A030 88#define SMIA0_MASK_D15XX 0xFFFF 89#define SMIA1_MASK_D15XX 0x1 90 91/* Error detection and correction */ 92#define AE_CTX_ENABLES_D15XX(i) ((i) * 0x1000 + 0x20818) 93#define AE_MISC_CONTROL_D15XX(i) ((i) * 0x1000 + 0x20960) 94#define ENABLE_AE_ECC_ERR_D15XX __BIT(28) 95#define ENABLE_AE_ECC_PARITY_CORR_D15XX (__BIT(24) | __BIT(12)) 96#define ERRSSMSH_EN_D15XX __BIT(3) 97/* BIT(2) enables the logging of push/pull data errors. */ 98#define PPERR_EN_D15XX (__BIT(2)) 99 100/* Mask for VF2PF interrupts */ 101#define VF2PF1_16_D15XX (0xFFFF << 9) 102#define ERRSOU3_VF2PF_D15XX(errsou3) (((errsou3) & 0x01FFFE00) >> 9) 103#define ERRMSK3_VF2PF_D15XX(vf_mask) (((vf_mask) & 0xFFFF) << 9) 104 105/* Masks for correctable error interrupts. */ 106#define ERRMSK0_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 107#define ERRMSK1_CERR_D15XX (__BIT(24) | __BIT(16) | __BIT(8) | __BIT(0)) 108#define ERRMSK3_CERR_D15XX (__BIT(7)) 109#define ERRMSK4_CERR_D15XX (__BIT(8) | __BIT(0)) 110#define ERRMSK5_CERR_D15XX (0) 111 112/* Masks for uncorrectable error interrupts. */ 113#define ERRMSK0_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 114#define ERRMSK1_UERR_D15XX (__BIT(25) | __BIT(17) | __BIT(9) | __BIT(1)) 115#define ERRMSK3_UERR_D15XX (__BIT(8) | __BIT(6) | __BIT(5) | __BIT(4) | \ 116 __BIT(3) | __BIT(2) | __BIT(0)) 117#define ERRMSK4_UERR_D15XX (__BIT(9) | __BIT(1)) 118#define ERRMSK5_UERR_D15XX (__BIT(18) | __BIT(17) | __BIT(16)) 119 120/* RI CPP control */ 121#define RICPPINTCTL_D15XX (0x3A000 + 0x110) 122/* 123 * BIT(2) enables error detection and reporting on the RI Parity Error. 124 * BIT(1) enables error detection and reporting on the RI CPP Pull interface. 125 * BIT(0) enables error detection and reporting on the RI CPP Push interface. 126 */ 127#define RICPP_EN_D15XX (__BIT(2) | __BIT(1) | __BIT(0)) 128 129/* TI CPP control */ 130#define TICPPINTCTL_D15XX (0x3A400 + 0x138) 131/* 132 * BIT(3) enables error detection and reporting on the ETR Parity Error. 133 * BIT(2) enables error detection and reporting on the TI Parity Error. 134 * BIT(1) enables error detection and reporting on the TI CPP Pull interface. 135 * BIT(0) enables error detection and reporting on the TI CPP Push interface. 136 */ 137#define TICPP_EN_D15XX \ 138 (__BIT(4) | __BIT(3) | __BIT(2) | __BIT(1) | __BIT(0)) 139 140/* CFC Uncorrectable Errors */ 141#define CPP_CFC_ERR_CTRL_D15XX (0x30000 + 0xC00) 142/* 143 * BIT(1) enables interrupt. 144 * BIT(0) enables detecting and logging of push/pull data errors. 145 */ 146#define CPP_CFC_UE_D15XX (__BIT(1) | __BIT(0)) 147 148/* Correctable SecureRAM Error Reg */ 149#define SECRAMCERR_D15XX (0x3AC00 + 0x00) 150/* BIT(3) enables fixing and logging of correctable errors. */ 151#define SECRAM_CERR_D15XX (__BIT(3)) 152 153/* Uncorrectable SecureRAM Error Reg */ 154/* 155 * BIT(17) enables interrupt. 156 * BIT(3) enables detecting and logging of uncorrectable errors. 157 */ 158#define SECRAM_UERR_D15XX (__BIT(17) | __BIT(3)) 159 160/* Miscellaneous Memory Target Errors Register */ 161/* 162 * BIT(3) enables detecting and logging push/pull data errors. 163 * BIT(2) enables interrupt. 164 */ 165#define TGT_UERR_D15XX (__BIT(3) | __BIT(2)) 166 167 168#define SLICEPWRDOWN_D15XX(i) ((i) * 0x4000 + 0x2C) 169/* Enabling PKE4-PKE0. */ 170#define MMP_PWR_UP_MSK_D15XX \ 171 (__BIT(20) | __BIT(19) | __BIT(18) | __BIT(17) | __BIT(16)) 172 173/* CPM Uncorrectable Errors */ 174#define INTMASKSSM_D15XX(i) ((i) * 0x4000 + 0x0) 175/* Disabling interrupts for correctable errors. */ 176#define INTMASKSSM_UERR_D15XX \ 177 (__BIT(11) | __BIT(9) | __BIT(7) | __BIT(5) | __BIT(3) | __BIT(1)) 178 179/* MMP */ 180/* BIT(3) enables correction. */ 181#define CERRSSMMMP_EN_D15XX (__BIT(3)) 182 183/* BIT(3) enables logging. */ 184#define UERRSSMMMP_EN_D15XX (__BIT(3)) 185 186/* ETR */ 187#define ETR_MAX_BANKS_D15XX 16 188#define ETR_TX_RX_GAP_D15XX 8 189#define ETR_TX_RINGS_MASK_D15XX 0xFF 190#define ETR_BUNDLE_SIZE_D15XX 0x1000 191 192/* AE firmware */ 193#define AE_FW_PROD_TYPE_D15XX 0x01000000 194#define AE_FW_MOF_NAME_D15XX "qat_d15xxfw" 195#define AE_FW_MMP_NAME_D15XX "qat_d15xx_mmp" 196#define AE_FW_UOF_NAME_D15XX "icp_qat_ae.suof" 197 198/* Clock frequency */ 199#define CLOCK_PER_SEC_D15XX (685 * 1000000 / 16) 200 201#endif 202