1/* SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-3-Clause */ 2/* $NetBSD: qatreg.h,v 1.1 2019/11/20 09:37:46 hikaru Exp $ */ 3 4/* 5 * Copyright (c) 2019 Internet Initiative Japan, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Copyright(c) 2007-2019 Intel Corporation. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 37 * * Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * * Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in 41 * the documentation and/or other materials provided with the 42 * distribution. 43 * * Neither the name of Intel Corporation nor the names of its 44 * contributors may be used to endorse or promote products derived 45 * from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 48 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 49 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 50 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 51 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 53 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60/* $FreeBSD$ */ 61 62#ifndef _DEV_PCI_QATREG_H_ 63#define _DEV_PCI_QATREG_H_ 64 65#define __BIT(__n) \ 66 (((uintmax_t)(__n) >= NBBY * sizeof(uintmax_t)) ? 0 : \ 67 ((uintmax_t)1 << (uintmax_t)((__n) & (NBBY * sizeof(uintmax_t) - 1)))) 68#define __BITS(__m, __n) \ 69 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) 70 71#define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) 72#define __SHIFTOUT(__x, __mask) (((__x) & (__mask)) / __LOWEST_SET_BIT(__mask)) 73#define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask)) 74 75/* Limits */ 76#define MAX_NUM_AE 0x10 77#define MAX_NUM_ACCEL 6 78#define MAX_AE 0x18 79#define MAX_AE_CTX 8 80#define MAX_ARB 4 81 82#define MAX_USTORE_PER_SEG 0x8000 /* 16k * 2 */ 83#define MAX_USTORE MAX_USTORE_PER_SEG 84 85#define MAX_AE_PER_ACCEL 4 /* XXX */ 86#define MAX_BANK_PER_ACCEL 16 /* XXX */ 87#define MAX_RING_PER_BANK 16 88 89#define MAX_XFER_REG 128 90#define MAX_GPR_REG 128 91#define MAX_NN_REG 128 92#define MAX_LMEM_REG 1024 93#define MAX_INP_STATE 16 94#define MAX_CAM_REG 16 95#define MAX_FIFO_QWADDR 160 96 97#define MAX_EXEC_INST 100 98#define UWORD_CPYBUF_SIZE 1024 /* micro-store copy buffer (bytes) */ 99#define INVLD_UWORD 0xffffffffffull /* invalid micro-instruction */ 100#define AEV2_PACKED_UWORD_BYTES 6 /* version 2 packed uword size */ 101#define UWORD_MASK 0xbffffffffffull /* micro-word mask without parity */ 102 103#define AE_ALL_CTX 0xff 104 105/* PCIe configuration space parameter */ 106#define NO_PCI_REG (-1) 107#define NO_REG_OFFSET 0 108 109#define MAX_BARS 3 110 111/* Fuse Control */ 112#define FUSECTL_REG 0x40 113#define FUSECTL_MASK __BIT(31) 114 115#define LEGFUSE_REG 0x4c 116#define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0) 117#define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1) 118#define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2) 119#define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3) 120#define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4) 121#define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT(5) 122#define LEGFUSE_ACCEL_MASK_SHA3_SLICE __BIT(6) 123 124/* -------------------------------------------------------------------------- */ 125/* PETRINGCSR region */ 126 127/* ETR parameters */ 128#define ETR_MAX_RINGS_PER_BANK 16 129 130/* ETR registers */ 131#define ETR_RING_CONFIG 0x0000 132#define ETR_RING_LBASE 0x0040 133#define ETR_RING_UBASE 0x0080 134#define ETR_RING_HEAD_OFFSET 0x00C0 135#define ETR_RING_TAIL_OFFSET 0x0100 136#define ETR_RING_STAT 0x0140 137#define ETR_UO_STAT 0x0148 138#define ETR_E_STAT 0x014C 139#define ETR_NE_STAT 0x0150 140#define ETR_NF_STAT 0x0154 141#define ETR_F_STAT 0x0158 142#define ETR_C_STAT 0x015C 143#define ETR_INT_EN 0x016C 144#define ETR_INT_REG 0x0170 145#define ETR_INT_SRCSEL 0x0174 146#define ETR_INT_SRCSEL_2 0x0178 147#define ETR_INT_COL_EN 0x017C 148#define ETR_INT_COL_CTL 0x0180 149#define ETR_AP_NF_MASK 0x2000 150#define ETR_AP_NF_DEST 0x2020 151#define ETR_AP_NE_MASK 0x2040 152#define ETR_AP_NE_DEST 0x2060 153#define ETR_AP_DELAY 0x2080 154 155/* ARB registers */ 156#define ARB_OFFSET 0x30000 157#define ARB_REG_SIZE 0x4 158#define ARB_WTR_SIZE 0x20 159#define ARB_REG_SLOT 0x1000 160#define ARB_WTR_OFFSET 0x010 161#define ARB_RO_EN_OFFSET 0x090 162#define ARB_WRK_2_SER_MAP_OFFSET 0x180 163#define ARB_RINGSRVARBEN_OFFSET 0x19c 164 165/* Ring Config */ 166#define ETR_RING_CONFIG_LATE_HEAD_POINTER_MODE __BIT(31) 167#define ETR_RING_CONFIG_NEAR_FULL_WM __BITS(14, 10) 168#define ETR_RING_CONFIG_NEAR_EMPTY_WM __BITS(9, 5) 169#define ETR_RING_CONFIG_RING_SIZE __BITS(4, 0) 170 171#define ETR_RING_CONFIG_NEAR_WM_0 0x00 172#define ETR_RING_CONFIG_NEAR_WM_4 0x01 173#define ETR_RING_CONFIG_NEAR_WM_8 0x02 174#define ETR_RING_CONFIG_NEAR_WM_16 0x03 175#define ETR_RING_CONFIG_NEAR_WM_32 0x04 176#define ETR_RING_CONFIG_NEAR_WM_64 0x05 177#define ETR_RING_CONFIG_NEAR_WM_128 0x06 178#define ETR_RING_CONFIG_NEAR_WM_256 0x07 179#define ETR_RING_CONFIG_NEAR_WM_512 0x08 180#define ETR_RING_CONFIG_NEAR_WM_1K 0x09 181#define ETR_RING_CONFIG_NEAR_WM_2K 0x0A 182#define ETR_RING_CONFIG_NEAR_WM_4K 0x0B 183#define ETR_RING_CONFIG_NEAR_WM_8K 0x0C 184#define ETR_RING_CONFIG_NEAR_WM_16K 0x0D 185#define ETR_RING_CONFIG_NEAR_WM_32K 0x0E 186#define ETR_RING_CONFIG_NEAR_WM_64K 0x0F 187#define ETR_RING_CONFIG_NEAR_WM_128K 0x10 188#define ETR_RING_CONFIG_NEAR_WM_256K 0x11 189#define ETR_RING_CONFIG_NEAR_WM_512K 0x12 190#define ETR_RING_CONFIG_NEAR_WM_1M 0x13 191#define ETR_RING_CONFIG_NEAR_WM_2M 0x14 192#define ETR_RING_CONFIG_NEAR_WM_4M 0x15 193 194#define ETR_RING_CONFIG_SIZE_64 0x00 195#define ETR_RING_CONFIG_SIZE_128 0x01 196#define ETR_RING_CONFIG_SIZE_256 0x02 197#define ETR_RING_CONFIG_SIZE_512 0x03 198#define ETR_RING_CONFIG_SIZE_1K 0x04 199#define ETR_RING_CONFIG_SIZE_2K 0x05 200#define ETR_RING_CONFIG_SIZE_4K 0x06 201#define ETR_RING_CONFIG_SIZE_8K 0x07 202#define ETR_RING_CONFIG_SIZE_16K 0x08 203#define ETR_RING_CONFIG_SIZE_32K 0x09 204#define ETR_RING_CONFIG_SIZE_64K 0x0A 205#define ETR_RING_CONFIG_SIZE_128K 0x0B 206#define ETR_RING_CONFIG_SIZE_256K 0x0C 207#define ETR_RING_CONFIG_SIZE_512K 0x0D 208#define ETR_RING_CONFIG_SIZE_1M 0x0E 209#define ETR_RING_CONFIG_SIZE_2M 0x0F 210#define ETR_RING_CONFIG_SIZE_4M 0x10 211 212/* Default Ring Config is Nearly Full = Full and Nearly Empty = Empty */ 213#define ETR_RING_CONFIG_BUILD(size) \ 214 (__SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \ 215 ETR_RING_CONFIG_NEAR_FULL_WM) | \ 216 __SHIFTIN(ETR_RING_CONFIG_NEAR_WM_0, \ 217 ETR_RING_CONFIG_NEAR_EMPTY_WM) | \ 218 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE)) 219 220/* Response Ring Configuration */ 221#define ETR_RING_CONFIG_BUILD_RESP(size, wm_nf, wm_ne) \ 222 (__SHIFTIN((wm_nf), ETR_RING_CONFIG_NEAR_FULL_WM) | \ 223 __SHIFTIN((wm_ne), ETR_RING_CONFIG_NEAR_EMPTY_WM) | \ 224 __SHIFTIN((size), ETR_RING_CONFIG_RING_SIZE)) 225 226/* Ring Base */ 227#define ETR_RING_BASE_BUILD(addr, size) \ 228 (((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) 229 230#define ETR_INT_REG_CLEAR_MASK 0xffff 231 232/* Initial bank Interrupt Source mask */ 233#define ETR_INT_SRCSEL_MASK 0x44444444UL 234 235#define ETR_INT_SRCSEL_NEXT_OFFSET 4 236 237#define ETR_RINGS_PER_INT_SRCSEL 8 238 239#define ETR_INT_COL_CTL_ENABLE __BIT(31) 240 241#define ETR_AP_NF_MASK_INIT 0xAAAAAAAA 242#define ETR_AP_NE_MASK_INIT 0x55555555 243 244/* Autopush destination AE bit */ 245#define ETR_AP_DEST_ENABLE __BIT(7) 246#define ETR_AP_DEST_AE __BITS(6, 2) 247#define ETR_AP_DEST_MAILBOX __BITS(1, 0) 248 249/* Autopush destination enable bit */ 250 251/* Autopush CSR Offset */ 252#define ETR_AP_BANK_OFFSET 4 253 254/* Autopush maximum rings per bank */ 255#define ETR_MAX_RINGS_PER_AP_BANK 32 256 257/* Maximum mailbox per acclerator */ 258#define ETR_MAX_MAILBOX_PER_ACCELERATOR 4 259 260/* Maximum AEs per mailbox */ 261#define ETR_MAX_AE_PER_MAILBOX 4 262 263/* Macro to get the ring's autopush bank number */ 264#define ETR_RING_AP_BANK_NUMBER(ring) ((ring) >> 5) 265 266/* Macro to get the ring's autopush mailbox number */ 267#define ETR_RING_AP_MAILBOX_NUMBER(ring) \ 268 (ETR_RING_AP_BANK_NUMBER(ring) % ETR_MAX_MAILBOX_PER_ACCELERATOR) 269 270/* Macro to get the ring number in the autopush bank */ 271#define ETR_RING_NUMBER_IN_AP_BANK(ring) \ 272 ((ring) % ETR_MAX_RINGS_PER_AP_BANK) 273 274#define ETR_RING_EMPTY_ENTRY_SIG (0x7F7F7F7F) 275 276/* -------------------------------------------------------------------------- */ 277/* CAP_GLOBAL_CTL region */ 278 279#define FCU_CTRL 0x8c0 280#define FCU_CTRL_CMD_NOOP 0 281#define FCU_CTRL_CMD_AUTH 1 282#define FCU_CTRL_CMD_LOAD 2 283#define FCU_CTRL_CMD_START 3 284#define FCU_CTRL_AE __BITS(8, 31) 285 286#define FCU_STATUS 0x8c4 287#define FCU_STATUS_STS __BITS(0, 2) 288#define FCU_STATUS_STS_NO 0 289#define FCU_STATUS_STS_VERI_DONE 1 290#define FCU_STATUS_STS_LOAD_DONE 2 291#define FCU_STATUS_STS_VERI_FAIL 3 292#define FCU_STATUS_STS_LOAD_FAIL 4 293#define FCU_STATUS_STS_BUSY 5 294#define FCU_STATUS_AUTHFWLD __BIT(8) 295#define FCU_STATUS_DONE __BIT(9) 296#define FCU_STATUS_LOADED_AE __BITS(22, 31) 297 298#define FCU_STATUS1 0x8c8 299 300#define FCU_DRAM_ADDR_LO 0x8cc 301#define FCU_DRAM_ADDR_HI 0x8d0 302#define FCU_RAMBASE_ADDR_HI 0x8d4 303#define FCU_RAMBASE_ADDR_LO 0x8d8 304 305#define FW_AUTH_WAIT_PERIOD 10 306#define FW_AUTH_MAX_RETRY 300 307 308#define CAP_GLOBAL_CTL_BASE 0xa00 309#define CAP_GLOBAL_CTL_MISC CAP_GLOBAL_CTL_BASE + 0x04 310#define CAP_GLOBAL_CTL_MISC_TIMESTAMP_EN __BIT(7) 311#define CAP_GLOBAL_CTL_RESET CAP_GLOBAL_CTL_BASE + 0x0c 312#define CAP_GLOBAL_CTL_RESET_MASK __BITS(31, 26) 313#define CAP_GLOBAL_CTL_RESET_ACCEL_MASK __BITS(25, 20) 314#define CAP_GLOBAL_CTL_RESET_AE_MASK __BITS(19, 0) 315#define CAP_GLOBAL_CTL_CLK_EN CAP_GLOBAL_CTL_BASE + 0x50 316#define CAP_GLOBAL_CTL_CLK_EN_ACCEL_MASK __BITS(25, 20) 317#define CAP_GLOBAL_CTL_CLK_EN_AE_MASK __BITS(19, 0) 318 319/* -------------------------------------------------------------------------- */ 320/* AE region */ 321#define UPC_MASK 0x1ffff 322#define USTORE_SIZE QAT_16K 323 324#define AE_LOCAL_AE_MASK __BITS(31, 12) 325#define AE_LOCAL_CSR_MASK __BITS(9, 0) 326 327/* AE_LOCAL registers */ 328/* Control Store Address Register */ 329#define USTORE_ADDRESS 0x000 330#define USTORE_ADDRESS_ECS __BIT(31) 331 332#define USTORE_ECC_BIT_0 44 333#define USTORE_ECC_BIT_1 45 334#define USTORE_ECC_BIT_2 46 335#define USTORE_ECC_BIT_3 47 336#define USTORE_ECC_BIT_4 48 337#define USTORE_ECC_BIT_5 49 338#define USTORE_ECC_BIT_6 50 339 340/* Control Store Data Lower Register */ 341#define USTORE_DATA_LOWER 0x004 342/* Control Store Data Upper Register */ 343#define USTORE_DATA_UPPER 0x008 344/* Control Store Error Status Register */ 345#define USTORE_ERROR_STATUS 0x00c 346/* Arithmetic Logic Unit Output Register */ 347#define ALU_OUT 0x010 348/* Context Arbiter Control Register */ 349#define CTX_ARB_CNTL 0x014 350#define CTX_ARB_CNTL_INIT 0x00000000 351/* Context Enables Register */ 352#define CTX_ENABLES 0x018 353#define CTX_ENABLES_INIT 0 354#define CTX_ENABLES_INUSE_CONTEXTS __BIT(31) 355#define CTX_ENABLES_CNTL_STORE_PARITY_ERROR __BIT(29) 356#define CTX_ENABLES_CNTL_STORE_PARITY_ENABLE __BIT(28) 357#define CTX_ENABLES_BREAKPOINT __BIT(27) 358#define CTX_ENABLES_PAR_ERR __BIT(25) 359#define CTX_ENABLES_NN_MODE __BIT(20) 360#define CTX_ENABLES_NN_RING_EMPTY __BIT(18) 361#define CTX_ENABLES_LMADDR_1_GLOBAL __BIT(17) 362#define CTX_ENABLES_LMADDR_0_GLOBAL __BIT(16) 363#define CTX_ENABLES_ENABLE __BITS(15,8) 364 365#define CTX_ENABLES_IGNORE_W1C_MASK \ 366 (~(CTX_ENABLES_PAR_ERR | \ 367 CTX_ENABLES_BREAKPOINT | \ 368 CTX_ENABLES_CNTL_STORE_PARITY_ERROR)) 369 370/* cycles from CTX_ENABLE high to CTX entering executing state */ 371#define CYCLES_FROM_READY2EXE 8 372 373/* Condition Code Enable Register */ 374#define CC_ENABLE 0x01c 375#define CC_ENABLE_INIT 0x2000 376 377/* CSR Context Pointer Register */ 378#define CSR_CTX_POINTER 0x020 379#define CSR_CTX_POINTER_CONTEXT __BITS(2,0) 380/* Register Error Status Register */ 381#define REG_ERROR_STATUS 0x030 382/* Indirect Context Status Register */ 383#define CTX_STS_INDIRECT 0x040 384#define CTX_STS_INDIRECT_UPC_INIT 0x00000000 385 386/* Active Context Status Register */ 387#define ACTIVE_CTX_STATUS 0x044 388#define ACTIVE_CTX_STATUS_ABO __BIT(31) 389#define ACTIVE_CTX_STATUS_ACNO __BITS(0, 2) 390/* Indirect Context Signal Events Register */ 391#define CTX_SIG_EVENTS_INDIRECT 0x048 392#define CTX_SIG_EVENTS_INDIRECT_INIT 0x00000001 393/* Active Context Signal Events Register */ 394#define CTX_SIG_EVENTS_ACTIVE 0x04c 395/* Indirect Context Wakeup Events Register */ 396#define CTX_WAKEUP_EVENTS_INDIRECT 0x050 397#define CTX_WAKEUP_EVENTS_INDIRECT_VOLUNTARY 0x00000001 398#define CTX_WAKEUP_EVENTS_INDIRECT_SLEEP 0x00010000 399 400#define CTX_WAKEUP_EVENTS_INDIRECT_INIT 0x00000001 401 402/* Active Context Wakeup Events Register */ 403#define CTX_WAKEUP_EVENTS_ACTIVE 0x054 404/* Indirect Context Future Count Register */ 405#define CTX_FUTURE_COUNT_INDIRECT 0x058 406/* Active Context Future Count Register */ 407#define CTX_FUTURE_COUNT_ACTIVE 0x05c 408/* Indirect Local Memory Address 0 Register */ 409#define LM_ADDR_0_INDIRECT 0x060 410/* Active Local Memory Address 0 Register */ 411#define LM_ADDR_0_ACTIVE 0x064 412/* Indirect Local Memory Address 1 Register */ 413#define LM_ADDR_1_INDIRECT 0x068 414/* Active Local Memory Address 1 Register */ 415#define LM_ADDR_1_ACTIVE 0x06c 416/* Byte Index Register */ 417#define BYTE_INDEX 0x070 418/* Indirect Local Memory Address 0 Byte Index Register */ 419#define INDIRECT_LM_ADDR_0_BYTE_INDEX 0x0e0 420/* Active Local Memory Address 0 Byte Index Register */ 421#define ACTIVE_LM_ADDR_0_BYTE_INDEX 0x0e4 422/* Indirect Local Memory Address 1 Byte Index Register */ 423#define INDIRECT_LM_ADDR_1_BYTE_INDEX 0x0e8 424/* Active Local Memory Address 1 Byte Index Register */ 425#define ACTIVE_LM_ADDR_1_BYTE_INDEX 0x0ec 426/* Transfer Index Concatenated with Byte Index Register */ 427#define T_INDEX_BYTE_INDEX 0x0f4 428/* Transfer Index Register */ 429#define T_INDEX 0x074 430/* Indirect Future Count Signal Signal Register */ 431#define FUTURE_COUNT_SIGNAL_INDIRECT 0x078 432/* Active Context Future Count Register */ 433#define FUTURE_COUNT_SIGNAL_ACTIVE 0x07c 434/* Next Neighbor Put Register */ 435#define NN_PUT 0x080 436/* Next Neighbor Get Register */ 437#define NN_GET 0x084 438/* Timestamp Low Register */ 439#define TIMESTAMP_LOW 0x0c0 440/* Timestamp High Register */ 441#define TIMESTAMP_HIGH 0x0c4 442/* Next Neighbor Signal Register */ 443#define NEXT_NEIGHBOR_SIGNAL 0x100 444/* Previous Neighbor Signal Register */ 445#define PREV_NEIGHBOR_SIGNAL 0x104 446/* Same AccelEngine Signal Register */ 447#define SAME_AE_SIGNAL 0x108 448/* Cyclic Redundancy Check Remainder Register */ 449#define CRC_REMAINDER 0x140 450/* Profile Count Register */ 451#define PROFILE_COUNT 0x144 452/* Pseudorandom Number Register */ 453#define PSEUDO_RANDOM_NUMBER 0x148 454/* Signature Enable Register */ 455#define SIGNATURE_ENABLE 0x150 456/* Miscellaneous Control Register */ 457#define AE_MISC_CONTROL 0x160 458#define AE_MISC_CONTROL_PARITY_ENABLE __BIT(24) 459#define AE_MISC_CONTROL_FORCE_BAD_PARITY __BIT(23) 460#define AE_MISC_CONTROL_ONE_CTX_RELOAD __BIT(22) 461#define AE_MISC_CONTROL_CS_RELOAD __BITS(21, 20) 462#define AE_MISC_CONTROL_SHARE_CS __BIT(2) 463/* Control Store Address 1 Register */ 464#define USTORE_ADDRESS1 0x158 465/* Local CSR Status Register */ 466#define LOCAL_CSR_STATUS 0x180 467#define LOCAL_CSR_STATUS_STATUS 0x1 468/* NULL Register */ 469#define NULL_CSR 0x3fc 470 471/* AE_XFER macros */ 472#define AE_XFER_AE_MASK __BITS(31, 12) 473#define AE_XFER_CSR_MASK __BITS(9, 2) 474 475#define AEREG_BAD_REGADDR 0xffff /* bad register address */ 476 477/* -------------------------------------------------------------------------- */ 478 479#define SSMWDT(i) ((i) * 0x4000 + 0x54) 480#define SSMWDTPKE(i) ((i) * 0x4000 + 0x58) 481#define INTSTATSSM(i) ((i) * 0x4000 + 0x04) 482#define INTSTATSSM_SHANGERR __BIT(13) 483#define PPERR(i) ((i) * 0x4000 + 0x08) 484#define PPERRID(i) ((i) * 0x4000 + 0x0C) 485#define CERRSSMSH(i) ((i) * 0x4000 + 0x10) 486#define UERRSSMSH(i) ((i) * 0x4000 + 0x18) 487#define UERRSSMSHAD(i) ((i) * 0x4000 + 0x1C) 488#define SLICEHANGSTATUS(i) ((i) * 0x4000 + 0x4C) 489#define SLICE_HANG_AUTH0_MASK __BIT(0) 490#define SLICE_HANG_AUTH1_MASK __BIT(1) 491#define SLICE_HANG_CPHR0_MASK __BIT(4) 492#define SLICE_HANG_CPHR1_MASK __BIT(5) 493#define SLICE_HANG_CMP0_MASK __BIT(8) 494#define SLICE_HANG_CMP1_MASK __BIT(9) 495#define SLICE_HANG_XLT0_MASK __BIT(12) 496#define SLICE_HANG_XLT1_MASK __BIT(13) 497#define SLICE_HANG_MMP0_MASK __BIT(16) 498#define SLICE_HANG_MMP1_MASK __BIT(17) 499#define SLICE_HANG_MMP2_MASK __BIT(18) 500#define SLICE_HANG_MMP3_MASK __BIT(19) 501#define SLICE_HANG_MMP4_MASK __BIT(20) 502 503#define SHINTMASKSSM(i) ((i) * 0x4000 + 0x1018) 504#define ENABLE_SLICE_HANG 0x000000 505#define MAX_MMP (5) 506#define MMP_BASE(i) ((i) * 0x1000 % 0x3800) 507#define CERRSSMMMP(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x380) 508#define UERRSSMMMP(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x388) 509#define UERRSSMMMPAD(i, n) ((i) * 0x4000 + MMP_BASE(n) + 0x38C) 510 511#define CPP_CFC_ERR_STATUS (0x30000 + 0xC04) 512#define CPP_CFC_ERR_PPID (0x30000 + 0xC08) 513 514#define ERRSOU0 (0x3A000 + 0x00) 515#define ERRSOU1 (0x3A000 + 0x04) 516#define ERRSOU2 (0x3A000 + 0x08) 517#define ERRSOU3 (0x3A000 + 0x0C) 518#define ERRSOU4 (0x3A000 + 0xD0) 519#define ERRSOU5 (0x3A000 + 0xD8) 520#define ERRMSK0 (0x3A000 + 0x10) 521#define ERRMSK1 (0x3A000 + 0x14) 522#define ERRMSK2 (0x3A000 + 0x18) 523#define ERRMSK3 (0x3A000 + 0x1C) 524#define ERRMSK4 (0x3A000 + 0xD4) 525#define ERRMSK5 (0x3A000 + 0xDC) 526#define EMSK3_CPM0_MASK __BIT(2) 527#define EMSK3_CPM1_MASK __BIT(3) 528#define EMSK5_CPM2_MASK __BIT(16) 529#define EMSK5_CPM3_MASK __BIT(17) 530#define EMSK5_CPM4_MASK __BIT(18) 531#define RICPPINTSTS (0x3A000 + 0x114) 532#define RIERRPUSHID (0x3A000 + 0x118) 533#define RIERRPULLID (0x3A000 + 0x11C) 534 535#define TICPPINTSTS (0x3A400 + 0x13C) 536#define TIERRPUSHID (0x3A400 + 0x140) 537#define TIERRPULLID (0x3A400 + 0x144) 538#define SECRAMUERR (0x3AC00 + 0x04) 539#define SECRAMUERRAD (0x3AC00 + 0x0C) 540#define CPPMEMTGTERR (0x3AC00 + 0x10) 541#define ERRPPID (0x3AC00 + 0x14) 542 543#define ADMINMSGUR 0x3a574 544#define ADMINMSGLR 0x3a578 545#define MAILBOX_BASE 0x20970 546#define MAILBOX_STRIDE 0x1000 547#define ADMINMSG_LEN 32 548 549/* -------------------------------------------------------------------------- */ 550static const uint8_t mailbox_const_tab[1024] __aligned(1024) = { 5510x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5520x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5530x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5540x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5550x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5560x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 5570x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 5580x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5590x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 5600x00, 0x00, 0x00, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 5610x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 5620x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x02, 0x00, 0x00, 5630x00, 0x00, 0x00, 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 5640x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 5650x00, 0x00, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 5660x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5670x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5680x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5690x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5700x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5710x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5720x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5730x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 5740x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5750x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 5760x54, 0x32, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5770x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x45, 0x23, 0x01, 0xef, 0xcd, 0xab, 5780x89, 0x98, 0xba, 0xdc, 0xfe, 0x10, 0x32, 0x54, 0x76, 0xc3, 0xd2, 0xe1, 0xf0, 5790x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5800x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 5810x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x05, 0x9e, 5820xd8, 0x36, 0x7c, 0xd5, 0x07, 0x30, 0x70, 0xdd, 0x17, 0xf7, 0x0e, 0x59, 0x39, 5830xff, 0xc0, 0x0b, 0x31, 0x68, 0x58, 0x15, 0x11, 0x64, 0xf9, 0x8f, 0xa7, 0xbe, 5840xfa, 0x4f, 0xa4, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5850x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xbb, 0x67, 0xae, 5860x85, 0x3c, 0x6e, 0xf3, 0x72, 0xa5, 0x4f, 0xf5, 0x3a, 0x51, 0x0e, 0x52, 0x7f, 5870x9b, 0x05, 0x68, 0x8c, 0x1f, 0x83, 0xd9, 0xab, 0x5b, 0xe0, 0xcd, 0x19, 0x05, 5880x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5890x00, 0x00, 0xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8, 0x62, 0x9a, 0x29, 5900x2a, 0x36, 0x7c, 0xd5, 0x07, 0x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17, 5910x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39, 0x67, 0x33, 0x26, 0x67, 0xff, 5920xc0, 0x0b, 0x31, 0x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11, 0xdb, 0x0c, 5930x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7, 0x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 5940xa4, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 5950x00, 0x00, 0x00, 0x00, 0x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08, 0xbb, 5960x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b, 0x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 5970xf8, 0x2b, 0xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1, 0x51, 0x0e, 0x52, 5980x7f, 0xad, 0xe6, 0x82, 0xd1, 0x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f, 5990x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b, 0x5b, 0xe0, 0xcd, 0x19, 0x13, 6000x7e, 0x21, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6010x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6020x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6030x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6040x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6050x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6060x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6070x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6080x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6090x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6100x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6110x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6120x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6130x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6140x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6150x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6160x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6170x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6180x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6190x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6200x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6210x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6220x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6230x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6240x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6250x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6260x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6270x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6280x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 6290x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; 630 631/* -------------------------------------------------------------------------- */ 632/* Microcode */ 633 634/* Clear GPR of AE */ 635static const uint64_t ae_clear_gprs_inst[] = { 636 0x0F0000C0000ull, /* .0 l0000!val = 0 ; immed[l0000!val, 0x0] */ 637 0x0F000000380ull, /* .1 l0000!count = 128 ; immed[l0000!count, 0x80] */ 638 0x0D805000011ull, /* .2 br!=ctx[0, ctx_init#] */ 639 0x0FC082C0300ull, /* .3 local_csr_wr[nn_put, 0] */ 640 0x0F0000C0300ull, /* .4 nop */ 641 0x0F0000C0300ull, /* .5 nop */ 642 0x0F0000C0300ull, /* .6 nop */ 643 0x0F0000C0300ull, /* .7 nop */ 644 0x0A0643C0000ull, /* .8 init_nn#:alu[*n$index++, --, b, l0000!val] */ 645 0x0BAC0000301ull, /* .9 alu[l0000!count, l0000!count, -, 1] */ 646 0x0D802000101ull, /* .10 bne[init_nn#] */ 647 0x0F0000C0001ull, /* .11 l0000!indx = 0 ; immed[l0000!indx, 0x0] */ 648 0x0FC066C0001ull, /* .12 local_csr_wr[active_lm_addr_0, l0000!indx]; 649 * put indx to lm_addr */ 650 0x0F0000C0300ull, /* .13 nop */ 651 0x0F0000C0300ull, /* .14 nop */ 652 0x0F0000C0300ull, /* .15 nop */ 653 0x0F000400300ull, /* .16 l0000!count = 1024 ; immed[l0000!count, 0x400] */ 654 0x0A0610C0000ull, /* .17 init_lm#:alu[*l$index0++, --, b, l0000!val] */ 655 0x0BAC0000301ull, /* .18 alu[l0000!count, l0000!count, -, 1] */ 656 0x0D804400101ull, /* .19 bne[init_lm#] */ 657 0x0A0580C0000ull, /* .20 ctx_init#:alu[$l0000!xfers[0], --, b, l0000!val] */ 658 0x0A0581C0000ull, /* .21 alu[$l0000!xfers[1], --, b, l0000!val] */ 659 0x0A0582C0000ull, /* .22 alu[$l0000!xfers[2], --, b, l0000!val] */ 660 0x0A0583C0000ull, /* .23 alu[$l0000!xfers[3], --, b, l0000!val] */ 661 0x0A0584C0000ull, /* .24 alu[$l0000!xfers[4], --, b, l0000!val] */ 662 0x0A0585C0000ull, /* .25 alu[$l0000!xfers[5], --, b, l0000!val] */ 663 0x0A0586C0000ull, /* .26 alu[$l0000!xfers[6], --, b, l0000!val] */ 664 0x0A0587C0000ull, /* .27 alu[$l0000!xfers[7], --, b, l0000!val] */ 665 0x0A0588C0000ull, /* .28 alu[$l0000!xfers[8], --, b, l0000!val] */ 666 0x0A0589C0000ull, /* .29 alu[$l0000!xfers[9], --, b, l0000!val] */ 667 0x0A058AC0000ull, /* .30 alu[$l0000!xfers[10], --, b, l0000!val] */ 668 0x0A058BC0000ull, /* .31 alu[$l0000!xfers[11], --, b, l0000!val] */ 669 0x0A058CC0000ull, /* .32 alu[$l0000!xfers[12], --, b, l0000!val] */ 670 0x0A058DC0000ull, /* .33 alu[$l0000!xfers[13], --, b, l0000!val] */ 671 0x0A058EC0000ull, /* .34 alu[$l0000!xfers[14], --, b, l0000!val] */ 672 0x0A058FC0000ull, /* .35 alu[$l0000!xfers[15], --, b, l0000!val] */ 673 0x0A05C0C0000ull, /* .36 alu[$l0000!xfers[16], --, b, l0000!val] */ 674 0x0A05C1C0000ull, /* .37 alu[$l0000!xfers[17], --, b, l0000!val] */ 675 0x0A05C2C0000ull, /* .38 alu[$l0000!xfers[18], --, b, l0000!val] */ 676 0x0A05C3C0000ull, /* .39 alu[$l0000!xfers[19], --, b, l0000!val] */ 677 0x0A05C4C0000ull, /* .40 alu[$l0000!xfers[20], --, b, l0000!val] */ 678 0x0A05C5C0000ull, /* .41 alu[$l0000!xfers[21], --, b, l0000!val] */ 679 0x0A05C6C0000ull, /* .42 alu[$l0000!xfers[22], --, b, l0000!val] */ 680 0x0A05C7C0000ull, /* .43 alu[$l0000!xfers[23], --, b, l0000!val] */ 681 0x0A05C8C0000ull, /* .44 alu[$l0000!xfers[24], --, b, l0000!val] */ 682 0x0A05C9C0000ull, /* .45 alu[$l0000!xfers[25], --, b, l0000!val] */ 683 0x0A05CAC0000ull, /* .46 alu[$l0000!xfers[26], --, b, l0000!val] */ 684 0x0A05CBC0000ull, /* .47 alu[$l0000!xfers[27], --, b, l0000!val] */ 685 0x0A05CCC0000ull, /* .48 alu[$l0000!xfers[28], --, b, l0000!val] */ 686 0x0A05CDC0000ull, /* .49 alu[$l0000!xfers[29], --, b, l0000!val] */ 687 0x0A05CEC0000ull, /* .50 alu[$l0000!xfers[30], --, b, l0000!val] */ 688 0x0A05CFC0000ull, /* .51 alu[$l0000!xfers[31], --, b, l0000!val] */ 689 0x0A0400C0000ull, /* .52 alu[l0000!gprega[0], --, b, l0000!val] */ 690 0x0B0400C0000ull, /* .53 alu[l0000!gpregb[0], --, b, l0000!val] */ 691 0x0A0401C0000ull, /* .54 alu[l0000!gprega[1], --, b, l0000!val] */ 692 0x0B0401C0000ull, /* .55 alu[l0000!gpregb[1], --, b, l0000!val] */ 693 0x0A0402C0000ull, /* .56 alu[l0000!gprega[2], --, b, l0000!val] */ 694 0x0B0402C0000ull, /* .57 alu[l0000!gpregb[2], --, b, l0000!val] */ 695 0x0A0403C0000ull, /* .58 alu[l0000!gprega[3], --, b, l0000!val] */ 696 0x0B0403C0000ull, /* .59 alu[l0000!gpregb[3], --, b, l0000!val] */ 697 0x0A0404C0000ull, /* .60 alu[l0000!gprega[4], --, b, l0000!val] */ 698 0x0B0404C0000ull, /* .61 alu[l0000!gpregb[4], --, b, l0000!val] */ 699 0x0A0405C0000ull, /* .62 alu[l0000!gprega[5], --, b, l0000!val] */ 700 0x0B0405C0000ull, /* .63 alu[l0000!gpregb[5], --, b, l0000!val] */ 701 0x0A0406C0000ull, /* .64 alu[l0000!gprega[6], --, b, l0000!val] */ 702 0x0B0406C0000ull, /* .65 alu[l0000!gpregb[6], --, b, l0000!val] */ 703 0x0A0407C0000ull, /* .66 alu[l0000!gprega[7], --, b, l0000!val] */ 704 0x0B0407C0000ull, /* .67 alu[l0000!gpregb[7], --, b, l0000!val] */ 705 0x0A0408C0000ull, /* .68 alu[l0000!gprega[8], --, b, l0000!val] */ 706 0x0B0408C0000ull, /* .69 alu[l0000!gpregb[8], --, b, l0000!val] */ 707 0x0A0409C0000ull, /* .70 alu[l0000!gprega[9], --, b, l0000!val] */ 708 0x0B0409C0000ull, /* .71 alu[l0000!gpregb[9], --, b, l0000!val] */ 709 0x0A040AC0000ull, /* .72 alu[l0000!gprega[10], --, b, l0000!val] */ 710 0x0B040AC0000ull, /* .73 alu[l0000!gpregb[10], --, b, l0000!val] */ 711 0x0A040BC0000ull, /* .74 alu[l0000!gprega[11], --, b, l0000!val] */ 712 0x0B040BC0000ull, /* .75 alu[l0000!gpregb[11], --, b, l0000!val] */ 713 0x0A040CC0000ull, /* .76 alu[l0000!gprega[12], --, b, l0000!val] */ 714 0x0B040CC0000ull, /* .77 alu[l0000!gpregb[12], --, b, l0000!val] */ 715 0x0A040DC0000ull, /* .78 alu[l0000!gprega[13], --, b, l0000!val] */ 716 0x0B040DC0000ull, /* .79 alu[l0000!gpregb[13], --, b, l0000!val] */ 717 0x0A040EC0000ull, /* .80 alu[l0000!gprega[14], --, b, l0000!val] */ 718 0x0B040EC0000ull, /* .81 alu[l0000!gpregb[14], --, b, l0000!val] */ 719 0x0A040FC0000ull, /* .82 alu[l0000!gprega[15], --, b, l0000!val] */ 720 0x0B040FC0000ull, /* .83 alu[l0000!gpregb[15], --, b, l0000!val] */ 721 0x0D81581C010ull, /* .84 br=ctx[7, exit#] */ 722 0x0E000010000ull, /* .85 ctx_arb[kill], any */ 723 0x0E000010000ull, /* .86 exit#:ctx_arb[kill], any */ 724}; 725 726static const uint64_t ae_inst_4b[] = { 727 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 728 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 729 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 730 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 731 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 732 l0000!indx]; put indx to lm_addr */ 733 0x0F0000C0300ull, /* .5 nop */ 734 0x0F0000C0300ull, /* .6 nop */ 735 0x0F0000C0300ull, /* .7 nop */ 736 0x0A021000000ull, /* .8 alu[*l$index0++, --, b, l0000!myvalue] */ 737}; 738 739static const uint64_t ae_inst_1b[] = { 740 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 741 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 742 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 743 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 744 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 745 l0000!indx]; put indx to lm_addr */ 746 0x0F0000C0300ull, /* .5 nop */ 747 0x0F0000C0300ull, /* .6 nop */ 748 0x0F0000C0300ull, /* .7 nop */ 749 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 750 0x09080000200ull, /* .9 alu_shf[l0000!myvalue, --, b, 751 l0000!myvalue, <<24 ] */ 752 0x08180280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<8 ] */ 753 0x08080280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>8 ] */ 754 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 755 756}; 757 758static const uint64_t ae_inst_2b[] = { 759 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 760 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 761 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 762 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 763 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 764 l0000!indx]; put indx to lm_addr */ 765 0x0F0000C0300ull, /* .5 nop */ 766 0x0F0000C0300ull, /* .6 nop */ 767 0x0F0000C0300ull, /* .7 nop */ 768 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 769 0x09100000200ull, /* .9 alu_shf[l0000!myvalue, --, b, 770 l0000!myvalue, <<16 ] */ 771 0x08100280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<16 ] */ 772 0x08100280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>16 ] */ 773 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 774}; 775 776static const uint64_t ae_inst_3b[] = { 777 0x0F0400C0000ull, /* .0 immed_w0[l0000!indx, 0] */ 778 0x0F4400C0000ull, /* .1 immed_w1[l0000!indx, 0] */ 779 0x0F040000300ull, /* .2 immed_w0[l0000!myvalue, 0x0] */ 780 0x0F440000300ull, /* .3 immed_w1[l0000!myvalue, 0x0] */ 781 0x0FC066C0000ull, /* .4 local_csr_wr[active_lm_addr_0, 782 l0000!indx]; put indx to lm_addr */ 783 0x0F0000C0300ull, /* .5 nop */ 784 0x0F0000C0300ull, /* .6 nop */ 785 0x0F0000C0300ull, /* .7 nop */ 786 0x0A000180000ull, /* .8 alu[l0000!val, --, b, *l$index0] */ 787 0x09180000200ull, /* .9 alu_shf[l0000!myvalue, --, 788 b, l0000!myvalue, <<8 ] */ 789 0x08080280201ull, /* .10 alu_shf[l0000!val1, --, b, l0000!val, <<24 ] */ 790 0x08180280102ull, /* .11 alu_shf[l0000!val1, --, b, l0000!val1 , >>24 ] */ 791 0x0BA00100002ull, /* .12 alu[l0000!val2, l0000!val1, or, l0000!myvalue] */ 792}; 793 794/* micro-instr fixup */ 795#define INSERT_IMMED_GPRA_CONST(inst, const_val) \ 796 inst = (inst & 0xFFFF00C03FFull) | \ 797 ((((const_val) << 12) & 0x0FF00000ull) | \ 798 (((const_val) << 10) & 0x0003FC00ull)) 799#define INSERT_IMMED_GPRB_CONST(inst, const_val) \ 800 inst = (inst & 0xFFFF00FFF00ull) | \ 801 ((((const_val) << 12) & 0x0FF00000ull) | \ 802 (((const_val) << 0) & 0x000000FFull)) 803 804enum aereg_type { 805 AEREG_NO_DEST, /* no destination */ 806 AEREG_GPA_REL, /* general-purpose A register under relative mode */ 807 AEREG_GPA_ABS, /* general-purpose A register under absolute mode */ 808 AEREG_GPB_REL, /* general-purpose B register under relative mode */ 809 AEREG_GPB_ABS, /* general-purpose B register under absolute mode */ 810 AEREG_SR_REL, /* sram register under relative mode */ 811 AEREG_SR_RD_REL, /* sram read register under relative mode */ 812 AEREG_SR_WR_REL, /* sram write register under relative mode */ 813 AEREG_SR_ABS, /* sram register under absolute mode */ 814 AEREG_SR_RD_ABS, /* sram read register under absolute mode */ 815 AEREG_SR_WR_ABS, /* sram write register under absolute mode */ 816 AEREG_SR0_SPILL, /* sram0 spill register */ 817 AEREG_SR1_SPILL, /* sram1 spill register */ 818 AEREG_SR2_SPILL, /* sram2 spill register */ 819 AEREG_SR3_SPILL, /* sram3 spill register */ 820 AEREG_SR0_MEM_ADDR, /* sram0 memory address register */ 821 AEREG_SR1_MEM_ADDR, /* sram1 memory address register */ 822 AEREG_SR2_MEM_ADDR, /* sram2 memory address register */ 823 AEREG_SR3_MEM_ADDR, /* sram3 memory address register */ 824 AEREG_DR_REL, /* dram register under relative mode */ 825 AEREG_DR_RD_REL, /* dram read register under relative mode */ 826 AEREG_DR_WR_REL, /* dram write register under relative mode */ 827 AEREG_DR_ABS, /* dram register under absolute mode */ 828 AEREG_DR_RD_ABS, /* dram read register under absolute mode */ 829 AEREG_DR_WR_ABS, /* dram write register under absolute mode */ 830 AEREG_DR_MEM_ADDR, /* dram memory address register */ 831 AEREG_LMEM, /* local memory */ 832 AEREG_LMEM0, /* local memory bank0 */ 833 AEREG_LMEM1, /* local memory bank1 */ 834 AEREG_LMEM_SPILL, /* local memory spill */ 835 AEREG_LMEM_ADDR, /* local memory address */ 836 AEREG_NEIGH_REL, /* next neighbour register under relative mode */ 837 AEREG_NEIGH_INDX, /* next neighbour register under index mode */ 838 AEREG_SIG_REL, /* signal register under relative mode */ 839 AEREG_SIG_INDX, /* signal register under index mode */ 840 AEREG_SIG_DOUBLE, /* signal register */ 841 AEREG_SIG_SINGLE, /* signal register */ 842 AEREG_SCRATCH_MEM_ADDR, /* scratch memory address */ 843 AEREG_UMEM0, /* ustore memory bank0 */ 844 AEREG_UMEM1, /* ustore memory bank1 */ 845 AEREG_UMEM_SPILL, /* ustore memory spill */ 846 AEREG_UMEM_ADDR, /* ustore memory address */ 847 AEREG_DR1_MEM_ADDR, /* dram segment1 address */ 848 AEREG_SR0_IMPORTED, /* sram segment0 imported data */ 849 AEREG_SR1_IMPORTED, /* sram segment1 imported data */ 850 AEREG_SR2_IMPORTED, /* sram segment2 imported data */ 851 AEREG_SR3_IMPORTED, /* sram segment3 imported data */ 852 AEREG_DR_IMPORTED, /* dram segment0 imported data */ 853 AEREG_DR1_IMPORTED, /* dram segment1 imported data */ 854 AEREG_SCRATCH_IMPORTED, /* scratch imported data */ 855 AEREG_XFER_RD_ABS, /* transfer read register under absolute mode */ 856 AEREG_XFER_WR_ABS, /* transfer write register under absolute mode */ 857 AEREG_CONST_VALUE, /* const alue */ 858 AEREG_ADDR_TAKEN, /* address taken */ 859 AEREG_OPTIMIZED_AWAY, /* optimized away */ 860 AEREG_SHRAM_ADDR, /* shared ram0 address */ 861 AEREG_SHRAM1_ADDR, /* shared ram1 address */ 862 AEREG_SHRAM2_ADDR, /* shared ram2 address */ 863 AEREG_SHRAM3_ADDR, /* shared ram3 address */ 864 AEREG_SHRAM4_ADDR, /* shared ram4 address */ 865 AEREG_SHRAM5_ADDR, /* shared ram5 address */ 866 AEREG_ANY = 0xffff /* any register */ 867}; 868#define AEREG_SR_INDX AEREG_SR_ABS 869 /* sram transfer register under index mode */ 870#define AEREG_DR_INDX AEREG_DR_ABS 871 /* dram transfer register under index mode */ 872#define AEREG_NEIGH_ABS AEREG_NEIGH_INDX 873 /* next neighbor register under absolute mode */ 874 875 876#define QAT_2K 0x0800 877#define QAT_4K 0x1000 878#define QAT_6K 0x1800 879#define QAT_8K 0x2000 880#define QAT_16K 0x4000 881 882#define MOF_OBJ_ID_LEN 8 883#define MOF_FID 0x00666f6d 884#define MOF_MIN_VER 0x1 885#define MOF_MAJ_VER 0x0 886#define SYM_OBJS "SYM_OBJS" /* symbol object string */ 887#define UOF_OBJS "UOF_OBJS" /* uof object string */ 888#define SUOF_OBJS "SUF_OBJS" /* suof object string */ 889#define SUOF_IMAG "SUF_IMAG" /* suof chunk ID string */ 890 891#define UOF_STRT "UOF_STRT" /* string table section ID */ 892#define UOF_GTID "UOF_GTID" /* GTID section ID */ 893#define UOF_IMAG "UOF_IMAG" /* image section ID */ 894#define UOF_IMEM "UOF_IMEM" /* import section ID */ 895#define UOF_MSEG "UOF_MSEG" /* memory section ID */ 896 897#define CRC_POLY 0x1021 898#define CRC_WIDTH 16 899#define CRC_BITMASK(x) (1L << (x)) 900#define CRC_WIDTHMASK(width) ((((1L<<(width-1))-1L)<<1)|1L) 901 902struct mof_file_hdr { 903 u_int mfh_fid; 904 u_int mfh_csum; 905 char mfh_min_ver; 906 char mfh_maj_ver; 907 u_short mfh_reserved; 908 u_short mfh_max_chunks; 909 u_short mfh_num_chunks; 910}; 911 912struct mof_file_chunk_hdr { 913 char mfch_id[MOF_OBJ_ID_LEN]; 914 uint64_t mfch_offset; 915 uint64_t mfch_size; 916}; 917 918struct mof_uof_hdr { 919 u_short muh_max_chunks; 920 u_short muh_num_chunks; 921 u_int muh_reserved; 922}; 923 924struct mof_uof_chunk_hdr { 925 char much_id[MOF_OBJ_ID_LEN]; /* should be UOF_IMAG */ 926 uint64_t much_offset; /* uof image */ 927 uint64_t much_size; /* uof image size */ 928 u_int much_name; /* uof name string-table offset */ 929 u_int much_reserved; 930}; 931 932#define UOF_MAX_NUM_OF_AE 16 /* maximum number of AE */ 933 934#define UOF_OBJ_ID_LEN 8 /* length of object ID */ 935#define UOF_FIELD_POS_SIZE 12 /* field postion size */ 936#define MIN_UOF_SIZE 24 /* minimum .uof file size */ 937#define UOF_FID 0xc6c2 /* uof magic number */ 938#define UOF_MIN_VER 0x11 939#define UOF_MAJ_VER 0x4 940 941struct uof_file_hdr { 942 u_short ufh_id; /* file id and endian indicator */ 943 u_short ufh_reserved1; /* reserved for future use */ 944 char ufh_min_ver; /* file format minor version */ 945 char ufh_maj_ver; /* file format major version */ 946 u_short ufh_reserved2; /* reserved for future use */ 947 u_short ufh_max_chunks; /* max chunks in file */ 948 u_short ufh_num_chunks; /* num of actual chunks */ 949}; 950 951struct uof_file_chunk_hdr { 952 char ufch_id[UOF_OBJ_ID_LEN]; /* chunk identifier */ 953 u_int ufch_csum; /* chunk checksum */ 954 u_int ufch_offset; /* offset of the chunk in the file */ 955 u_int ufch_size; /* size of the chunk */ 956}; 957 958struct uof_obj_hdr { 959 u_int uoh_cpu_type; /* CPU type */ 960 u_short uoh_min_cpu_ver; /* starting CPU version */ 961 u_short uoh_max_cpu_ver; /* ending CPU version */ 962 short uoh_max_chunks; /* max chunks in chunk obj */ 963 short uoh_num_chunks; /* num of actual chunks */ 964 u_int uoh_reserved1; 965 u_int uoh_reserved2; 966}; 967 968struct uof_chunk_hdr { 969 char uch_id[UOF_OBJ_ID_LEN]; 970 u_int uch_offset; 971 u_int uch_size; 972}; 973 974struct uof_str_tab { 975 u_int ust_table_len; /* length of table */ 976 u_int ust_reserved; /* reserved for future use */ 977 uint64_t ust_strings; /* pointer to string table. 978 * NULL terminated strings */ 979}; 980 981#define AE_MODE_RELOAD_CTX_SHARED __BIT(12) 982#define AE_MODE_SHARED_USTORE __BIT(11) 983#define AE_MODE_LMEM1 __BIT(9) 984#define AE_MODE_LMEM0 __BIT(8) 985#define AE_MODE_NN_MODE __BITS(7, 4) 986#define AE_MODE_CTX_MODE __BITS(3, 0) 987 988#define AE_MODE_NN_MODE_NEIGH 0 989#define AE_MODE_NN_MODE_SELF 1 990#define AE_MODE_NN_MODE_DONTCARE 0xff 991 992struct uof_image { 993 u_int ui_name; /* image name */ 994 u_int ui_ae_assigned; /* AccelEngines assigned */ 995 u_int ui_ctx_assigned; /* AccelEngine contexts assigned */ 996 u_int ui_cpu_type; /* cpu type */ 997 u_int ui_entry_address; /* entry uaddress */ 998 u_int ui_fill_pattern[2]; /* uword fill value */ 999 u_int ui_reloadable_size; /* size of reloadable ustore section */ 1000 1001 u_char ui_sensitivity; /* 1002 * case sensitivity: 0 = insensitive, 1003 * 1 = sensitive 1004 */ 1005 u_char ui_reserved; /* reserved for future use */ 1006 u_short ui_ae_mode; /* 1007 * unused<15:14>, legacyMode<13>, 1008 * reloadCtxShared<12>, sharedUstore<11>, 1009 * ecc<10>, locMem1<9>, locMem0<8>, 1010 * nnMode<7:4>, ctx<3:0> 1011 */ 1012 1013 u_short ui_max_ver; /* max cpu ver on which the image can run */ 1014 u_short ui_min_ver; /* min cpu ver on which the image can run */ 1015 1016 u_short ui_image_attrib; /* image attributes */ 1017 u_short ui_reserved2; /* reserved for future use */ 1018 1019 u_short ui_num_page_regions; /* number of page regions */ 1020 u_short ui_num_pages; /* number of pages */ 1021 1022 u_int ui_reg_tab; /* offset to register table */ 1023 u_int ui_init_reg_sym_tab; /* reg/sym init table */ 1024 u_int ui_sbreak_tab; /* offset to sbreak table */ 1025 1026 u_int ui_app_metadata; /* application meta-data */ 1027 /* ui_npages of code page follows this header */ 1028}; 1029 1030struct uof_obj_table { 1031 u_int uot_nentries; /* number of table entries */ 1032 /* uot_nentries of object follows */ 1033}; 1034 1035struct uof_ae_reg { 1036 u_int uar_name; /* reg name string-table offset */ 1037 u_int uar_vis_name; /* reg visible name string-table offset */ 1038 u_short uar_type; /* reg type */ 1039 u_short uar_addr; /* reg address */ 1040 u_short uar_access_mode; /* uof_RegAccessMode_T: read/write/both/undef */ 1041 u_char uar_visible; /* register visibility */ 1042 u_char uar_reserved1; /* reserved for future use */ 1043 u_short uar_ref_count; /* number of contiguous registers allocated */ 1044 u_short uar_reserved2; /* reserved for future use */ 1045 u_int uar_xoid; /* xfer order ID */ 1046}; 1047 1048enum uof_value_kind { 1049 UNDEF_VAL, /* undefined value */ 1050 CHAR_VAL, /* character value */ 1051 SHORT_VAL, /* short value */ 1052 INT_VAL, /* integer value */ 1053 STR_VAL, /* string value */ 1054 STRTAB_VAL, /* string table value */ 1055 NUM_VAL, /* number value */ 1056 EXPR_VAL /* expression value */ 1057}; 1058 1059enum uof_init_type { 1060 INIT_EXPR, 1061 INIT_REG, 1062 INIT_REG_CTX, 1063 INIT_EXPR_ENDIAN_SWAP 1064}; 1065 1066struct uof_init_reg_sym { 1067 u_int uirs_name; /* symbol name */ 1068 char uirs_init_type; /* 0=expr, 1=register, 2=ctxReg, 1069 * 3=expr_endian_swap */ 1070 char uirs_value_type; /* EXPR_VAL, STRTAB_VAL */ 1071 char uirs_reg_type; /* register type: ae_reg_type */ 1072 u_char uirs_ctx; /* AE context when initType=2 */ 1073 u_int uirs_addr_offset; /* reg address, or sym-value offset */ 1074 u_int uirs_value; /* integer value, or expression */ 1075}; 1076 1077struct uof_sbreak { 1078 u_int us_page_num; /* page number */ 1079 u_int us_virt_uaddr; /* virt uaddress */ 1080 u_char us_sbreak_type; /* sbreak type */ 1081 u_char us_reg_type; /* register type: ae_reg_type */ 1082 u_short us_reserved1; /* reserved for future use */ 1083 u_int us_addr_offset; /* branch target address or offset 1084 * to be used with the reg value to 1085 * calculate the target address */ 1086 u_int us_reg_rddr; /* register address */ 1087}; 1088struct uof_code_page { 1089 u_int ucp_page_region; /* page associated region */ 1090 u_int ucp_page_num; /* code-page number */ 1091 u_char ucp_def_page; /* default page indicator */ 1092 u_char ucp_reserved2; /* reserved for future use */ 1093 u_short ucp_reserved1; /* reserved for future use */ 1094 u_int ucp_beg_vaddr; /* starting virtual uaddr */ 1095 u_int ucp_beg_paddr; /* starting physical uaddr */ 1096 u_int ucp_neigh_reg_tab; /* offset to neighbour-reg table */ 1097 u_int ucp_uc_var_tab; /* offset to uC var table */ 1098 u_int ucp_imp_var_tab; /* offset to import var table */ 1099 u_int ucp_imp_expr_tab; /* offset to import expression table */ 1100 u_int ucp_code_area; /* offset to code area */ 1101}; 1102 1103struct uof_code_area { 1104 u_int uca_num_micro_words; /* number of micro words */ 1105 u_int uca_uword_block_tab; /* offset to ublock table */ 1106}; 1107 1108struct uof_uword_block { 1109 u_int uub_start_addr; /* start address */ 1110 u_int uub_num_words; /* number of microwords */ 1111 u_int uub_uword_offset; /* offset to the uwords */ 1112 u_int uub_reserved; /* reserved for future use */ 1113}; 1114 1115struct uof_uword_fixup { 1116 u_int uuf_name; /* offset to string table */ 1117 u_int uuf_uword_address; /* micro word address */ 1118 u_int uuf_expr_value; /* string table offset of expr string, or value */ 1119 u_char uuf_val_type; /* VALUE_UNDEF, VALUE_NUM, VALUE_EXPR */ 1120 u_char uuf_value_attrs; /* bit<0> (Scope: 0=global, 1=local), 1121 * bit<1> (init: 0=no, 1=yes) */ 1122 u_short uuf_reserved1; /* reserved for future use */ 1123 char uuf_field_attrs[UOF_FIELD_POS_SIZE]; 1124 /* field pos, size, and right shift value */ 1125}; 1126 1127struct uof_import_var { 1128 u_int uiv_name; /* import var name string-table offset */ 1129 u_char uiv_value_attrs; /* bit<0> (Scope: 0=global), 1130 * bit<1> (init: 0=no, 1=yes) */ 1131 u_char uiv_reserved1; /* reserved for future use */ 1132 u_short uiv_reserved2; /* reserved for future use */ 1133 uint64_t uiv_value; /* 64-bit imported value */ 1134}; 1135 1136struct uof_mem_val_attr { 1137 u_int umva_byte_offset; /* byte-offset from the allocated memory */ 1138 u_int umva_value; /* memory value */ 1139}; 1140 1141enum uof_mem_region { 1142 SRAM_REGION, /* SRAM region */ 1143 DRAM_REGION, /* DRAM0 region */ 1144 DRAM1_REGION, /* DRAM1 region */ 1145 LMEM_REGION, /* local memory region */ 1146 SCRATCH_REGION, /* SCRATCH region */ 1147 UMEM_REGION, /* micro-store region */ 1148 RAM_REGION, /* RAM region */ 1149 SHRAM_REGION, /* shared memory-0 region */ 1150 SHRAM1_REGION, /* shared memory-1 region */ 1151 SHRAM2_REGION, /* shared memory-2 region */ 1152 SHRAM3_REGION, /* shared memory-3 region */ 1153 SHRAM4_REGION, /* shared memory-4 region */ 1154 SHRAM5_REGION /* shared memory-5 region */ 1155}; 1156 1157#define UOF_SCOPE_GLOBAL 0 1158#define UOF_SCOPE_LOCAL 1 1159 1160struct uof_init_mem { 1161 u_int uim_sym_name; /* symbol name */ 1162 char uim_region; /* memory region -- uof_mem_region */ 1163 char uim_scope; /* visibility scope */ 1164 u_short uim_reserved1; /* reserved for future use */ 1165 u_int uim_addr; /* memory address */ 1166 u_int uim_num_bytes; /* number of bytes */ 1167 u_int uim_num_val_attr; /* number of values attributes */ 1168 1169 /* uim_num_val_attr of uof_mem_val_attr follows this header */ 1170}; 1171 1172struct uof_var_mem_seg { 1173 u_int uvms_sram_base; /* SRAM memory segment base addr */ 1174 u_int uvms_sram_size; /* SRAM segment size bytes */ 1175 u_int uvms_sram_alignment; /* SRAM segment alignment bytes */ 1176 u_int uvms_sdram_base; /* DRAM0 memory segment base addr */ 1177 u_int uvms_sdram_size; /* DRAM0 segment size bytes */ 1178 u_int uvms_sdram_alignment; /* DRAM0 segment alignment bytes */ 1179 u_int uvms_sdram1_base; /* DRAM1 memory segment base addr */ 1180 u_int uvms_sdram1_size; /* DRAM1 segment size bytes */ 1181 u_int uvms_sdram1_alignment; /* DRAM1 segment alignment bytes */ 1182 u_int uvms_scratch_base; /* SCRATCH memory segment base addr */ 1183 u_int uvms_scratch_size; /* SCRATCH segment size bytes */ 1184 u_int uvms_scratch_alignment; /* SCRATCH segment alignment bytes */ 1185}; 1186 1187#define SUOF_OBJ_ID_LEN 8 1188#define SUOF_FID 0x53554f46 1189#define SUOF_MAJ_VER 0x0 1190#define SUOF_MIN_VER 0x1 1191#define SIMG_AE_INIT_SEQ_LEN (50 * sizeof(unsigned long long)) 1192#define SIMG_AE_INSTS_LEN (0x4000 * sizeof(unsigned long long)) 1193#define CSS_FWSK_MODULUS_LEN 256 1194#define CSS_FWSK_EXPONENT_LEN 4 1195#define CSS_FWSK_PAD_LEN 252 1196#define CSS_FWSK_PUB_LEN (CSS_FWSK_MODULUS_LEN + \ 1197 CSS_FWSK_EXPONENT_LEN + \ 1198 CSS_FWSK_PAD_LEN) 1199#define CSS_SIGNATURE_LEN 256 1200#define CSS_AE_IMG_LEN (sizeof(struct simg_ae_mode) + \ 1201 SIMG_AE_INIT_SEQ_LEN + \ 1202 SIMG_AE_INSTS_LEN) 1203#define CSS_AE_SIMG_LEN (sizeof(struct css_hdr) + \ 1204 CSS_FWSK_PUB_LEN + \ 1205 CSS_SIGNATURE_LEN + \ 1206 CSS_AE_IMG_LEN) 1207#define AE_IMG_OFFSET (sizeof(struct css_hdr) + \ 1208 CSS_FWSK_MODULUS_LEN + \ 1209 CSS_FWSK_EXPONENT_LEN + \ 1210 CSS_SIGNATURE_LEN) 1211#define CSS_MAX_IMAGE_LEN 0x40000 1212 1213struct fw_auth_desc { 1214 u_int fad_img_len; 1215 u_int fad_reserved; 1216 u_int fad_css_hdr_high; 1217 u_int fad_css_hdr_low; 1218 u_int fad_img_high; 1219 u_int fad_img_low; 1220 u_int fad_signature_high; 1221 u_int fad_signature_low; 1222 u_int fad_fwsk_pub_high; 1223 u_int fad_fwsk_pub_low; 1224 u_int fad_img_ae_mode_data_high; 1225 u_int fad_img_ae_mode_data_low; 1226 u_int fad_img_ae_init_data_high; 1227 u_int fad_img_ae_init_data_low; 1228 u_int fad_img_ae_insts_high; 1229 u_int fad_img_ae_insts_low; 1230}; 1231 1232struct auth_chunk { 1233 struct fw_auth_desc ac_fw_auth_desc; 1234 uint64_t ac_chunk_size; 1235 uint64_t ac_chunk_bus_addr; 1236}; 1237 1238enum css_fwtype { 1239 CSS_AE_FIRMWARE = 0, 1240 CSS_MMP_FIRMWARE = 1 1241}; 1242 1243struct css_hdr { 1244 u_int css_module_type; 1245 u_int css_header_len; 1246 u_int css_header_ver; 1247 u_int css_module_id; 1248 u_int css_module_vendor; 1249 u_int css_date; 1250 u_int css_size; 1251 u_int css_key_size; 1252 u_int css_module_size; 1253 u_int css_exponent_size; 1254 u_int css_fw_type; 1255 u_int css_reserved[21]; 1256}; 1257 1258struct simg_ae_mode { 1259 u_int sam_file_id; 1260 u_short sam_maj_ver; 1261 u_short sam_min_ver; 1262 u_int sam_dev_type; 1263 u_short sam_devmax_ver; 1264 u_short sam_devmin_ver; 1265 u_int sam_ae_mask; 1266 u_int sam_ctx_enables; 1267 char sam_fw_type; 1268 char sam_ctx_mode; 1269 char sam_nn_mode; 1270 char sam_lm0_mode; 1271 char sam_lm1_mode; 1272 char sam_scs_mode; 1273 char sam_lm2_mode; 1274 char sam_lm3_mode; 1275 char sam_tindex_mode; 1276 u_char sam_reserved[7]; 1277 char sam_simg_name[256]; 1278 char sam_appmeta_data[256]; 1279}; 1280 1281struct suof_file_hdr { 1282 u_int sfh_file_id; 1283 u_int sfh_check_sum; 1284 char sfh_min_ver; 1285 char sfh_maj_ver; 1286 char sfh_fw_type; 1287 char sfh_reserved; 1288 u_short sfh_max_chunks; 1289 u_short sfh_num_chunks; 1290}; 1291 1292struct suof_chunk_hdr { 1293 char sch_chunk_id[SUOF_OBJ_ID_LEN]; 1294 uint64_t sch_offset; 1295 uint64_t sch_size; 1296}; 1297 1298struct suof_str_tab { 1299 u_int sst_tab_length; 1300 u_int sst_strings; 1301}; 1302 1303struct suof_obj_hdr { 1304 u_int soh_img_length; 1305 u_int soh_reserved; 1306}; 1307 1308/* -------------------------------------------------------------------------- */ 1309/* accel */ 1310 1311enum fw_slice { 1312 FW_SLICE_NULL = 0, /* NULL slice type */ 1313 FW_SLICE_CIPHER = 1, /* CIPHER slice type */ 1314 FW_SLICE_AUTH = 2, /* AUTH slice type */ 1315 FW_SLICE_DRAM_RD = 3, /* DRAM_RD Logical slice type */ 1316 FW_SLICE_DRAM_WR = 4, /* DRAM_WR Logical slice type */ 1317 FW_SLICE_COMP = 5, /* Compression slice type */ 1318 FW_SLICE_XLAT = 6, /* Translator slice type */ 1319 FW_SLICE_DELIMITER /* End delimiter */ 1320}; 1321#define MAX_FW_SLICE FW_SLICE_DELIMITER 1322 1323#define QAT_OPTIMAL_ALIGN_SHIFT 6 1324#define QAT_OPTIMAL_ALIGN (1 << QAT_OPTIMAL_ALIGN_SHIFT) 1325 1326enum hw_auth_algo { 1327 HW_AUTH_ALGO_NULL = 0, /* Null hashing */ 1328 HW_AUTH_ALGO_SHA1 = 1, /* SHA1 hashing */ 1329 HW_AUTH_ALGO_MD5 = 2, /* MD5 hashing */ 1330 HW_AUTH_ALGO_SHA224 = 3, /* SHA-224 hashing */ 1331 HW_AUTH_ALGO_SHA256 = 4, /* SHA-256 hashing */ 1332 HW_AUTH_ALGO_SHA384 = 5, /* SHA-384 hashing */ 1333 HW_AUTH_ALGO_SHA512 = 6, /* SHA-512 hashing */ 1334 HW_AUTH_ALGO_AES_XCBC_MAC = 7, /* AES-XCBC-MAC hashing */ 1335 HW_AUTH_ALGO_AES_CBC_MAC = 8, /* AES-CBC-MAC hashing */ 1336 HW_AUTH_ALGO_AES_F9 = 9, /* AES F9 hashing */ 1337 HW_AUTH_ALGO_GALOIS_128 = 10, /* Galois 128 bit hashing */ 1338 HW_AUTH_ALGO_GALOIS_64 = 11, /* Galois 64 hashing */ 1339 HW_AUTH_ALGO_KASUMI_F9 = 12, /* Kasumi F9 hashing */ 1340 HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, /* UIA2/SNOW_3H F9 hashing */ 1341 HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, 1342 HW_AUTH_RESERVED_1 = 15, 1343 HW_AUTH_RESERVED_2 = 16, 1344 HW_AUTH_ALGO_SHA3_256 = 17, 1345 HW_AUTH_RESERVED_3 = 18, 1346 HW_AUTH_ALGO_SHA3_512 = 19, 1347 HW_AUTH_ALGO_DELIMITER = 20 1348}; 1349 1350enum hw_auth_mode { 1351 HW_AUTH_MODE0, 1352 HW_AUTH_MODE1, 1353 HW_AUTH_MODE2, 1354 HW_AUTH_MODE_DELIMITER 1355}; 1356 1357struct hw_auth_config { 1358 uint32_t config; 1359 /* Configuration used for setting up the slice */ 1360 uint32_t reserved; 1361 /* Reserved */ 1362}; 1363 1364#define HW_AUTH_CONFIG_SHA3_ALGO __BITS(22, 23) 1365#define HW_AUTH_CONFIG_SHA3_PADDING __BIT(16) 1366#define HW_AUTH_CONFIG_CMPLEN __BITS(14, 8) 1367 /* The length of the digest if the QAT is to the check*/ 1368#define HW_AUTH_CONFIG_MODE __BITS(7, 4) 1369#define HW_AUTH_CONFIG_ALGO __BITS(3, 0) 1370 1371#define HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \ 1372 __SHIFTIN(mode, HW_AUTH_CONFIG_MODE) | \ 1373 __SHIFTIN(algo, HW_AUTH_CONFIG_ALGO) | \ 1374 __SHIFTIN(cmp_len, HW_AUTH_CONFIG_CMPLEN) 1375 1376struct hw_auth_counter { 1377 uint32_t counter; /* Counter value */ 1378 uint32_t reserved; /* Reserved */ 1379}; 1380 1381struct hw_auth_setup { 1382 struct hw_auth_config auth_config; 1383 /* Configuration word for the auth slice */ 1384 struct hw_auth_counter auth_counter; 1385 /* Auth counter value for this request */ 1386}; 1387 1388#define HW_NULL_STATE1_SZ 32 1389#define HW_MD5_STATE1_SZ 16 1390#define HW_SHA1_STATE1_SZ 20 1391#define HW_SHA224_STATE1_SZ 32 1392#define HW_SHA256_STATE1_SZ 32 1393#define HW_SHA3_256_STATE1_SZ 32 1394#define HW_SHA384_STATE1_SZ 64 1395#define HW_SHA512_STATE1_SZ 64 1396#define HW_SHA3_512_STATE1_SZ 64 1397#define HW_SHA3_224_STATE1_SZ 28 1398#define HW_SHA3_384_STATE1_SZ 48 1399#define HW_AES_XCBC_MAC_STATE1_SZ 16 1400#define HW_AES_CBC_MAC_STATE1_SZ 16 1401#define HW_AES_F9_STATE1_SZ 32 1402#define HW_KASUMI_F9_STATE1_SZ 16 1403#define HW_GALOIS_128_STATE1_SZ 16 1404#define HW_SNOW_3G_UIA2_STATE1_SZ 8 1405#define HW_ZUC_3G_EIA3_STATE1_SZ 8 1406#define HW_NULL_STATE2_SZ 32 1407#define HW_MD5_STATE2_SZ 16 1408#define HW_SHA1_STATE2_SZ 20 1409#define HW_SHA224_STATE2_SZ 32 1410#define HW_SHA256_STATE2_SZ 32 1411#define HW_SHA3_256_STATE2_SZ 0 1412#define HW_SHA384_STATE2_SZ 64 1413#define HW_SHA512_STATE2_SZ 64 1414#define HW_SHA3_512_STATE2_SZ 0 1415#define HW_SHA3_224_STATE2_SZ 0 1416#define HW_SHA3_384_STATE2_SZ 0 1417#define HW_AES_XCBC_MAC_KEY_SZ 16 1418#define HW_AES_CBC_MAC_KEY_SZ 16 1419#define HW_AES_CCM_CBC_E_CTR0_SZ 16 1420#define HW_F9_IK_SZ 16 1421#define HW_F9_FK_SZ 16 1422#define HW_KASUMI_F9_STATE2_SZ (HW_F9_IK_SZ + HW_F9_FK_SZ) 1423#define HW_AES_F9_STATE2_SZ HW_KASUMI_F9_STATE2_SZ 1424#define HW_SNOW_3G_UIA2_STATE2_SZ 24 1425#define HW_ZUC_3G_EIA3_STATE2_SZ 32 1426#define HW_GALOIS_H_SZ 16 1427#define HW_GALOIS_LEN_A_SZ 8 1428#define HW_GALOIS_E_CTR0_SZ 16 1429 1430struct hw_auth_sha512 { 1431 struct hw_auth_setup inner_setup; 1432 /* Inner loop configuration word for the slice */ 1433 uint8_t state1[HW_SHA512_STATE1_SZ]; 1434 /* Slice state1 variable */ 1435 struct hw_auth_setup outer_setup; 1436 /* Outer configuration word for the slice */ 1437 uint8_t state2[HW_SHA512_STATE2_SZ]; 1438 /* Slice state2 variable */ 1439}; 1440 1441union hw_auth_algo_blk { 1442 struct hw_auth_sha512 max; 1443 /* This is the largest possible auth setup block size */ 1444}; 1445 1446enum hw_cipher_algo { 1447 HW_CIPHER_ALGO_NULL = 0, /* Null ciphering */ 1448 HW_CIPHER_ALGO_DES = 1, /* DES ciphering */ 1449 HW_CIPHER_ALGO_3DES = 2, /* 3DES ciphering */ 1450 HW_CIPHER_ALGO_AES128 = 3, /* AES-128 ciphering */ 1451 HW_CIPHER_ALGO_AES192 = 4, /* AES-192 ciphering */ 1452 HW_CIPHER_ALGO_AES256 = 5, /* AES-256 ciphering */ 1453 HW_CIPHER_ALGO_ARC4 = 6, /* ARC4 ciphering */ 1454 HW_CIPHER_ALGO_KASUMI = 7, /* Kasumi */ 1455 HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8, /* Snow_3G */ 1456 HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9, 1457 HW_CIPHER_DELIMITER = 10 /* Delimiter type */ 1458}; 1459 1460enum hw_cipher_mode { 1461 HW_CIPHER_ECB_MODE = 0, /* ECB mode */ 1462 HW_CIPHER_CBC_MODE = 1, /* CBC mode */ 1463 HW_CIPHER_CTR_MODE = 2, /* CTR mode */ 1464 HW_CIPHER_F8_MODE = 3, /* F8 mode */ 1465 HW_CIPHER_XTS_MODE = 6, 1466 HW_CIPHER_MODE_DELIMITER = 7 /* Delimiter type */ 1467}; 1468 1469struct hw_cipher_config { 1470 uint32_t val; /* Cipher slice configuration */ 1471 uint32_t reserved; /* Reserved */ 1472}; 1473 1474#define CIPHER_CONFIG_CONVERT __BIT(9) 1475#define CIPHER_CONFIG_DIR __BIT(8) 1476#define CIPHER_CONFIG_MODE __BITS(7, 4) 1477#define CIPHER_CONFIG_ALGO __BITS(3, 0) 1478#define HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ 1479 __SHIFTIN(mode, CIPHER_CONFIG_MODE) | \ 1480 __SHIFTIN(algo, CIPHER_CONFIG_ALGO) | \ 1481 __SHIFTIN(convert, CIPHER_CONFIG_CONVERT) | \ 1482 __SHIFTIN(dir, CIPHER_CONFIG_DIR) 1483 1484enum hw_cipher_dir { 1485 HW_CIPHER_ENCRYPT = 0, /* encryption is required */ 1486 HW_CIPHER_DECRYPT = 1, /* decryption is required */ 1487}; 1488 1489enum hw_cipher_convert { 1490 HW_CIPHER_NO_CONVERT = 0, /* no key convert is required*/ 1491 HW_CIPHER_KEY_CONVERT = 1, /* key conversion is required*/ 1492}; 1493 1494#define CIPHER_MODE_F8_KEY_SZ_MULT 2 1495#define CIPHER_MODE_XTS_KEY_SZ_MULT 2 1496 1497#define HW_DES_BLK_SZ 8 1498#define HW_3DES_BLK_SZ 8 1499#define HW_NULL_BLK_SZ 8 1500#define HW_AES_BLK_SZ 16 1501#define HW_KASUMI_BLK_SZ 8 1502#define HW_SNOW_3G_BLK_SZ 8 1503#define HW_ZUC_3G_BLK_SZ 8 1504#define HW_NULL_KEY_SZ 256 1505#define HW_DES_KEY_SZ 8 1506#define HW_3DES_KEY_SZ 24 1507#define HW_AES_128_KEY_SZ 16 1508#define HW_AES_192_KEY_SZ 24 1509#define HW_AES_256_KEY_SZ 32 1510#define HW_AES_128_F8_KEY_SZ (HW_AES_128_KEY_SZ * \ 1511 CIPHER_MODE_F8_KEY_SZ_MULT) 1512#define HW_AES_192_F8_KEY_SZ (HW_AES_192_KEY_SZ * \ 1513 CIPHER_MODE_F8_KEY_SZ_MULT) 1514#define HW_AES_256_F8_KEY_SZ (HW_AES_256_KEY_SZ * \ 1515 CIPHER_MODE_F8_KEY_SZ_MULT) 1516#define HW_AES_128_XTS_KEY_SZ (HW_AES_128_KEY_SZ * \ 1517 CIPHER_MODE_XTS_KEY_SZ_MULT) 1518#define HW_AES_256_XTS_KEY_SZ (HW_AES_256_KEY_SZ * \ 1519 CIPHER_MODE_XTS_KEY_SZ_MULT) 1520#define HW_KASUMI_KEY_SZ 16 1521#define HW_KASUMI_F8_KEY_SZ (HW_KASUMI_KEY_SZ * \ 1522 CIPHER_MODE_F8_KEY_SZ_MULT) 1523#define HW_AES_128_XTS_KEY_SZ (HW_AES_128_KEY_SZ * \ 1524 CIPHER_MODE_XTS_KEY_SZ_MULT) 1525#define HW_AES_256_XTS_KEY_SZ (HW_AES_256_KEY_SZ * \ 1526 CIPHER_MODE_XTS_KEY_SZ_MULT) 1527#define HW_ARC4_KEY_SZ 256 1528#define HW_SNOW_3G_UEA2_KEY_SZ 16 1529#define HW_SNOW_3G_UEA2_IV_SZ 16 1530#define HW_ZUC_3G_EEA3_KEY_SZ 16 1531#define HW_ZUC_3G_EEA3_IV_SZ 16 1532#define HW_MODE_F8_NUM_REG_TO_CLEAR 2 1533 1534struct hw_cipher_aes256_f8 { 1535 struct hw_cipher_config cipher_config; 1536 /* Cipher configuration word for the slice set to 1537 * AES-256 and the F8 mode */ 1538 uint8_t key[HW_AES_256_F8_KEY_SZ]; 1539 /* Cipher key */ 1540}; 1541 1542union hw_cipher_algo_blk { 1543 struct hw_cipher_aes256_f8 max; /* AES-256 F8 Cipher */ 1544 /* This is the largest possible cipher setup block size */ 1545}; 1546 1547struct flat_buffer_desc { 1548 uint32_t data_len_in_bytes; 1549 uint32_t reserved; 1550 uint64_t phy_buffer; 1551}; 1552 1553struct buffer_list_desc { 1554 uint64_t resrvd; 1555 uint32_t num_buffers; 1556 uint32_t reserved; 1557}; 1558 1559/* -------------------------------------------------------------------------- */ 1560/* look aside */ 1561 1562enum fw_la_cmd_id { 1563 FW_LA_CMD_CIPHER, /* Cipher Request */ 1564 FW_LA_CMD_AUTH, /* Auth Request */ 1565 FW_LA_CMD_CIPHER_HASH, /* Cipher-Hash Request */ 1566 FW_LA_CMD_HASH_CIPHER, /* Hash-Cipher Request */ 1567 FW_LA_CMD_TRNG_GET_RANDOM, /* TRNG Get Random Request */ 1568 FW_LA_CMD_TRNG_TEST, /* TRNG Test Request */ 1569 FW_LA_CMD_SSL3_KEY_DERIVE, /* SSL3 Key Derivation Request */ 1570 FW_LA_CMD_TLS_V1_1_KEY_DERIVE, /* TLS Key Derivation Request */ 1571 FW_LA_CMD_TLS_V1_2_KEY_DERIVE, /* TLS Key Derivation Request */ 1572 FW_LA_CMD_MGF1, /* MGF1 Request */ 1573 FW_LA_CMD_AUTH_PRE_COMP, /* Auth Pre-Compute Request */ 1574#if 0 /* incompatible between qat 1.5 and 1.7 */ 1575 FW_LA_CMD_CIPHER_CIPHER, /* Cipher-Cipher Request */ 1576 FW_LA_CMD_HASH_HASH, /* Hash-Hash Request */ 1577 FW_LA_CMD_CIPHER_PRE_COMP, /* Auth Pre-Compute Request */ 1578#endif 1579 FW_LA_CMD_DELIMITER, /* Delimiter type */ 1580}; 1581 1582#endif 1583