Searched refs:V0 (Results 1 - 25 of 54) sorted by relevance

123

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp71 unsigned V0, V1; local
77 V0 = RegInfo.createVirtualRegister(RC);
88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
117 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
141 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
144 MF.getRegInfo().addLiveIn(Mips::V0);
[all...]
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
78 V0 = RegInfo.createVirtualRegister(RC);
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
H A DMipsAsmPrinter.cpp959 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
962 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
965 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
968 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
H A DMipsBranchExpansion.cpp724 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
726 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
727 .addReg(Mips::V0)
729 MBB.removeLiveIn(Mips::V0);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31)
80 if (R >= Hexagon::V0 && R <= Hexagon::V31) {
85 return S[R-Hexagon::V0];
182 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
183 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');
187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,
H A DHexagonISelDAGToDAG.cpp2158 SDValue V0 = L0.Value; local
2164 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) ||
2170 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0);
2176 std::swap(V0, V1);
2181 assert(NodeHeights.count(V0) && NodeHeights.count(V1) &&
2183 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1;
2188 ISD::SHL, SDLoc(V0), VT, V0,
2191 TLI.getScalarShiftAmountTy(DL, V0
2216 SDValue V0 = NewRoot.getOperand(0); local
[all...]
H A DHexagonISelLoweringHVX.cpp888 SDValue V0, V1; local
893 V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV);
910 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV});
914 // the vectors V0 or V1. Set SingleV to the correct one, and update
918 SingleV = DAG.getNode(ISD::SELECT, dl, SingleTy, PickHi, V1, V0);
957 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV});
1042 SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); local
1044 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1);
1112 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, local
1116 return DAG.getNode(HexagonISD::QCAT, dl, VecTy, V0, V
[all...]
H A DHexagonRegisterInfo.cpp69 V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
/freebsd-12-stable/lib/msun/src/
H A De_j1.c134 static const double V0[5] = { variable
192 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
H A De_j1f.c96 static const float V0[5] = { variable
147 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4]))));
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp470 Constant *V0 = ConstantFP::get(CI->getContext(), APFloat(0.0f)); local
474 V0 = ConstantExpr::getFPExtend(V0, Exp->getType());
477 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0);
/freebsd-12-stable/sys/mips/include/
H A Dregnum.h58 #define V0 2 macro
/freebsd-12-stable/sys/mips/mips/
H A Dcpu.c81 _ENCODE_INSN(0, T0, T1, V0, OP_DADDU)
93 _ENCODE_INSN(0, T0, T1, V0, OP_ADDU)
100 _ENCODE_INSN(OP_COP0, OP_DMT, V0, 4, 2)
105 _ENCODE_INSN(OP_COP0, OP_MT, V0, 4, 2)
H A Dexception.S279 SAVE_REG(v0, V0, sp) ;\
340 RESTORE_REG(v0, V0, sp) ;\
438 SAVE_U_PCB_REG(v0, V0, k1)
533 RESTORE_U_PCB_REG(v0, V0, k1)
703 SAVE_U_PCB_REG(v0, V0, k1)
822 RESTORE_U_PCB_REG(v0, V0, k1)
H A Dswtch.S100 RESTORE_U_PCB_REG(v0, V0, k1)
/freebsd-12-stable/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DDarwin.h419 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0, argument
422 return TargetVersion < VersionTuple(V0, V1, V2);
425 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const { argument
427 return TargetVersion < VersionTuple(V0, V1, V2);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp298 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
299 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
300 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
301 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
304 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
305 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
306 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1776 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { argument
1777 SDLoc dl(V0.getNode());
1782 const SDValue Ops[] = { RegClass, V0, SubReg
1787 createSRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1798 createDRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1809 createQRegPairNode(EVT VT, SDValue V0, SDValue V1) argument
1820 createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1835 createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1850 createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
2205 SDValue V0 = N->getOperand(Vec0Idx + 0); local
2261 SDValue V0 = N->getOperand(Vec0Idx + 0); local
2378 SDValue V0 = N->getOperand(Vec0Idx + 0); local
4956 SDValue V0 = N->getOperand(i+1); local
[all...]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineVectorOps.cpp66 Value *V0, *V1;
67 if (match(V, m_OneUse(m_BinOp(m_Value(V0), m_Value(V1)))))
68 if (cheapToScalarize(V0, IsConstantExtractIndex) ||
73 if (match(V, m_OneUse(m_Cmp(UnusedPred, m_Value(V0), m_Value(V1)))))
74 if (cheapToScalarize(V0, IsConstantExtractIndex) ||
204 // inselt <2 x i32> V, <i32> S, 1: |V0|V1|V2|V3|S0|S1|S2|S3|
1420 Value *V0 = nullptr, Value *V1 = nullptr) :
1421 Opcode(Opc), Op0(V0), Op1(V1) {}
1747 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); local
1754 if (NumElts != (int)(V0
[all...]
H A DInstCombineAddSub.cpp390 Value *V0 = I->getOperand(0); local
392 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) {
398 Addend0.set(C, V0);
468 Value *V0 = I->getOperand(0); local
470 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) &&
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h399 return Reg >= PPC::V0 && Reg <= PPC::V31;
476 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31,
480 return PPC::VSX32 + (Reg - PPC::V0);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp222 SDValue V0 = N->getOperand(i+1); local
224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
/freebsd-12-stable/sys/geom/raid/
H A Dmd_ddf.h269 uint8_t V0[32]; member in struct:ddf_vdc_record
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.cpp103 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp126 Value *V0 = I->getOperand(0); local
129 if (match(V0, m_APInt(C)))
130 std::swap(V0, V1);
134 SymbolicPart = V0;
934 Value *V0 = Sub->getOperand(0);
935 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) ||
936 isReassociableOp(V0, Instruction::Sub, Instruction::FSub))
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp735 Value *V0 = ResList[i], *V1 = ResList[i + 1]; local
736 assert((V0->getType() == V1->getType() || i == NumVecs - 2) &&
739 TmpList.push_back(concatenateTwoVectors(Builder, V0, V1));

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