Searched refs:MLX5_ST_SZ_DW (Results 1 - 25 of 39) sorted by relevance

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/freebsd-12-stable/sys/dev/mlx5/mlx5_core/
H A Dmlx5_pd.c35 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
36 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
52 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0};
53 u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0};
H A Dmlx5_transobj.c35 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
36 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
52 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0};
53 u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0};
64 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
78 u32 out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
87 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0};
88 u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0};
98 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
109 u32 out[MLX5_ST_SZ_DW(create_sq_ou
[all...]
H A Dmlx5_mcg.c36 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0};
37 u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0};
50 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0};
51 u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0};
H A Dmlx5_port.c72 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
85 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {};
97 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {};
148 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
165 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
184 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
201 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
202 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
229 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
248 u32 out[MLX5_ST_SZ_DW(ptys_re
[all...]
H A Dmlx5_mr.c59 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
125 u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0};
126 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0};
148 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0};
161 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0};
162 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0};
188 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0};
189 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0};
213 u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0};
214 u32 in[MLX5_ST_SZ_DW(destroy_psv_i
[all...]
H A Dmlx5_fs_cmd.c41 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {0};
42 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {0};
60 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0};
61 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0};
90 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0};
91 u32 out[MLX5_ST_SZ_DW(destroy_flow_table_out)] = {0};
114 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0};
141 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {0};
142 u32 out[MLX5_ST_SZ_DW(destroy_flow_group_out)] = {0};
170 u32 out[MLX5_ST_SZ_DW(set_fte_ou
[all...]
H A Dmlx5_mpfs.c47 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {};
48 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {};
89 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {};
90 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {};
H A Dmlx5_fw.c35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
239 u32 in[MLX5_ST_SZ_DW(init_hca_in)];
240 u32 out[MLX5_ST_SZ_DW(init_hca_out)];
252 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
253 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
261 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
262 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
291 u32 out[MLX5_ST_SZ_DW(teardown_hca_ou
[all...]
H A Dmlx5_qp.c125 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
126 u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)] = {0};
127 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {0};
158 u32 out[MLX5_ST_SZ_DW(destroy_qp_out)] = {0};
159 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {0};
316 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {0};
327 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {0};
328 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {0};
341 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {0};
342 u32 out[MLX5_ST_SZ_DW(dealloc_xrcd_ou
[all...]
H A Dmlx5_cq.c129 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {0};
130 u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)] = {0};
167 u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0};
168 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0};
194 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
207 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0};
219 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0};
239 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0};
H A Dflow_table.h39 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
H A Dmlx5_uar.c36 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0};
37 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
54 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0};
55 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
H A Dmlx5_vport.c40 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {0};
58 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0};
68 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0};
79 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {0};
80 u32 out[MLX5_ST_SZ_DW(modify_vport_state_out)] = {0};
104 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
134 u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
135 u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
159 u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {0};
160 u32 out[MLX5_ST_SZ_DW(dealloc_q_counter_ou
[all...]
H A Dmlx5_srq.c285 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0};
317 u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0};
318 u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0};
329 u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0};
358 u32 srq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0};
359 u32 srq_out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0};
H A Dmlx5_rl.c61 u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {};
62 u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {};
H A Dmlx5_eq.c91 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
92 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
424 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
632 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
H A Dmlx5_pagealloc.c299 u32 in[MLX5_ST_SZ_DW(query_pages_in)] = {0};
300 u32 out[MLX5_ST_SZ_DW(query_pages_out)] = {0};
321 u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0};
419 u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0};
H A Dmlx5_main.c218 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
219 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
417 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
530 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
531 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
540 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
541 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
549 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
550 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
574 u32 set_in[MLX5_ST_SZ_DW(set_issi_i
[all...]
H A Dmlx5_eswitch.c90 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
91 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
119 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
134 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
172 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
187 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
/freebsd-12-stable/sys/dev/mlx5/mlx5_fpga/
H A Dmlx5fpga_cmd.c42 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
77 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
86 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
87 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
130 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
131 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
153 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
154 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
171 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
172 u32 out[MLX5_ST_SZ_DW(fpga_ctr
[all...]
H A Dconn.h52 u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
/freebsd-12-stable/sys/dev/mlx5/
H A Dfs.h73 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
74 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
210 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
211 u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
217 u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
H A Ddriver.h676 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
677 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
678 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
679 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
/freebsd-12-stable/sys/dev/mlx5/mlx5_lib/
H A Dmlx5_gid.c128 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
129 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
/freebsd-12-stable/sys/dev/mlx5/mlx5_fpga_tools/
H A Dmlx5fpga_tools_char.c194 CTASSERT(MLX5_FPGA_CAP_ARR_SZ == MLX5_ST_SZ_DW(fpga_cap));
205 u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0};

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