Lines Matching refs:MLX5_ST_SZ_DW
35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
239 u32 in[MLX5_ST_SZ_DW(init_hca_in)];
240 u32 out[MLX5_ST_SZ_DW(init_hca_out)];
252 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
253 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
261 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
262 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
291 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
292 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
337 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
338 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
365 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
366 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
383 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
384 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
410 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
441 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
442 int offset = MLX5_ST_SZ_DW(mcqi_reg);
443 u32 in[MLX5_ST_SZ_DW(mcqi_reg)];