Searched refs:FP0 (Results 1 - 7 of 7) sorted by relevance
| /freebsd-12-stable/contrib/gdb/gdb/ |
| H A D | dpx2-nat.c | 43 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 101 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133 Mask |= 1 << (Reg - X86::FP0);
161 // The first entries correspond to FP0-FP6, the rest are scratch registers
318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
319 return Reg - X86::FP0;
330 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
333 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
365 // The actual value is passed in FP0
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| H A D | X86FastISel.cpp | 1218 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3567 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) &&
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| H A D | X86ISelLowering.cpp | 2700 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2707 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
2712 if (VA.getLocReg() == X86::FP0 ||
3025 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3033 VA.convertToReg(X86::FP0); // Set reg to FP0, avoid hitting asserts.
3039 if ((VA.getLocReg() == X86::FP0 || V
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| /freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 116 {codeview::RegisterId::ST0, X86::FP0},
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| /freebsd-12-stable/sys/dev/drm2/i915/ |
| H A D | i915_reg.h | 1048 #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0) macro
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| H A D | intel_display.c | 4299 I915_WRITE(FP0(pipe), fp);
4753 * by using the FP0/FP1. In such case we will disable the LVDS
5304 * by using the FP0/FP1. In such case we will disable the LVDS
6838 fp = I915_READ(FP0(pipe));
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