Lines Matching refs:FP0
101 // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133 Mask |= 1 << (Reg - X86::FP0);
161 // The first entries correspond to FP0-FP6, the rest are scratch registers
318 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
319 return Reg - X86::FP0;
330 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
333 if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
365 // The actual value is passed in FP0.
366 // Here we fix the stack and mark FP0 as pre-assigned register.
368 "Only FP0 could be passed as an argument");
472 static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
473 if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
474 LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
475 freeStackSlotAfter(I, Reg-X86::FP0);
984 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1001 // FP0
1025 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1127 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1188 bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1298 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1299 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1393 bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1394 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1419 bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1484 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1541 unsigned STReg = MO.getReg() - X86::FP0;
1610 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1639 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1708 unsigned Reg = MO.getReg() - X86::FP0;