Searched refs:CSR_WRITE_2 (Results 1 - 25 of 68) sorted by relevance

123

/freebsd-12-stable/sys/dev/ep/
H A Dif_ep.c145 CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND,
409 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
411 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
415 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);
418 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
424 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
425 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
434 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
436 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
437 CSR_WRITE_2(s
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H A Dif_ep_pccard.c168 CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, result & 0xc000);
177 CSR_WRITE_2(sc, EP_W0_PRODUCT_ID, sc->epb.prod_id);
184 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
186 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0xc040);
187 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
188 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
191 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
H A Dif_epvar.h91 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-12-stable/sys/dev/bm/
H A Dif_bm.c174 CSR_WRITE_2(sc, BM_MII_CSR, val);
230 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
244 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
920 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
927 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
933 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
960 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
961 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
962 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
963 CSR_WRITE_2(s
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H A Dif_bmreg.h159 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/sn/
H A Dif_sn.c282 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
284 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
288 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
296 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
302 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
308 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
331 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
448 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
498 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
504 CSR_WRITE_2(s
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H A Dif_snvar.h64 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-12-stable/sys/dev/vx/
H A Dif_vx.c165 CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);
182 CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD
243 CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
245 CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
252 CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
254 CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
263 CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);
268 CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);
269 CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
289 CSR_WRITE_2(s
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H A Dif_vxvar.h64 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/ex/
H A Dif_ex.c384 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
386 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
387 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
503 CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
504 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
505 CSR_WRITE_2(sc, IO_PORT_REG, 0);
506 CSR_WRITE_2(sc, IO_PORT_REG, next);
507 CSR_WRITE_2(sc, IO_PORT_REG, data_len);
538 CSR_WRITE_2(sc, HOST_ADDR_REG,
540 CSR_WRITE_2(s
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H A Dif_exvar.h101 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-12-stable/sys/dev/xl/
H A Dif_xl.c411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
579 CSR_WRITE_2(sc, XL_W0_EE_CMD,
648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
711 CSR_WRITE_2(sc, XL_COMMAND,
720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
828 CSR_WRITE_2(s
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/freebsd-12-stable/sys/dev/vte/
H A Dif_vte.c180 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
204 CSR_WRITE_2(sc, VTE_MMWD, val);
205 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
261 CSR_WRITE_2(sc, VTE_MRICR, val);
269 CSR_WRITE_2(sc, VTE_MTICR, val);
1161 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1257 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1358 CSR_WRITE_2(sc, VTE_MIER, 0);
1379 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1578 CSR_WRITE_2(s
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H A Dif_vtevar.h151 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/wi/
H A Dif_wi_pci.c156 CSR_WRITE_2(sc, WI_INT_EN, 0);
157 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
204 CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET);
207 CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000);
222 CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC);
H A Dif_wi_macio.c138 CSR_WRITE_2(sc, WI_INT_EN, 0);
139 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
H A Dif_wi.c567 CSR_WRITE_2(sc, WI_INT_EN, 0);
568 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
574 CSR_WRITE_2(sc, WI_INT_EN, 0);
589 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
600 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
675 CSR_WRITE_2(sc, WI_INT_EN, 0);
1120 CSR_WRITE_2(sc, WI_INT_EN, 0);
1121 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
1271 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX);
1282 CSR_WRITE_2(s
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/freebsd-12-stable/sys/dev/bwi/
H A Dbwimac.c219 CSR_WRITE_2(sc, data_reg, v);
232 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
236 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
280 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
351 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
368 CSR_WRITE_2(sc, 0x60e, 0);
369 CSR_WRITE_2(sc, 0x610, 0x8000);
370 CSR_WRITE_2(sc, 0x604, 0);
371 CSR_WRITE_2(sc, 0x606, 0x200);
395 CSR_WRITE_2(s
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H A Dbwirf.c203 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
204 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
222 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
253 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
257 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
356 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
586 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
788 CSR_WRITE_2(s
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H A Dbwiphy.c141 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
142 CSR_WRITE_2(sc, BWI_PHY_DATA, data);
150 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
443 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
453 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
490 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
537 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
561 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
569 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
723 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/an/
H A Dif_an.c341 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
342 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
1206 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1209 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350));
1212 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC);
1221 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1226 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1231 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY);
1236 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1241 CSR_WRITE_2(s
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/freebsd-12-stable/sys/dev/vge/
H A Dif_vgevar.h221 #define CSR_WRITE_2(sc, reg, val) \ macro
236 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
243 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-12-stable/sys/dev/ste/
H A Dif_ste.c193 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
196 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
300 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
397 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
450 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
451 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
452 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
453 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
554 CSR_WRITE_2(sc, STE_COUNTDOWN,
581 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/tx/
H A Dif_txvar.h134 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/tl/
H A Dif_tl.c380 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
406 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
420 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
434 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
437 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
448 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
464 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
484 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
503 CSR_WRITE_2(s
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