dev/vx/if_vx.c

165 	CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);
182 		CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD
243 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
245 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
252 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
254 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
263 	CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);
268 	CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);
269 	CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
289 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER |
398 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);
401 	CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, 0);
407 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, ENABLE_UTP);
410 		CSR_WRITE_2(sc, VX_COMMAND, START_TRANSCEIVER);
416 		CSR_WRITE_2(sc, VX_W4_MEDIA_TYPE, LINKBEAT_ENABLE);
477 		CSR_WRITE_2(sc, VX_COMMAND,
486 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_AVAIL_THRESH | (8188 >> 2));
492 	CSR_WRITE_2(sc, VX_COMMAND, SET_TX_START_THRESH |
634 			CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
650 		CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);
664 		CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | status);
805 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
890 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
1004 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISABLE);
1005 	CSR_WRITE_2(sc, VX_COMMAND, RX_DISCARD_TOP_PACK);
1007 	CSR_WRITE_2(sc, VX_COMMAND, TX_DISABLE);
1008 	CSR_WRITE_2(sc, VX_COMMAND, STOP_TRANSCEIVER);
1010 	CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
1012 	CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
1014 	CSR_WRITE_2(sc, VX_COMMAND, C_INTR_LATCH);
1015 	CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK);
1016 	CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK);
1017 	CSR_WRITE_2(sc, VX_COMMAND, SET_RX_FILTER);