Lines Matching refs:CSR_WRITE_2
180 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
204 CSR_WRITE_2(sc, VTE_MMWD, val);
205 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
261 CSR_WRITE_2(sc, VTE_MRICR, val);
269 CSR_WRITE_2(sc, VTE_MTICR, val);
1161 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1257 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1358 CSR_WRITE_2(sc, VTE_MIER, 0);
1379 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1578 CSR_WRITE_2(sc, VTE_MRDCR, prog |
1610 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1623 CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1624 CSR_WRITE_2(sc, VTE_MACSM, 0);
1681 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1682 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1683 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1687 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1688 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1691 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1692 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1699 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1712 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1715 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1726 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1733 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1740 CSR_WRITE_2(sc, VTE_MRICR, 0);
1741 CSR_WRITE_2(sc, VTE_MTICR, 0);
1744 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1749 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1750 CSR_WRITE_2(sc, VTE_MISR, 0);
1781 CSR_WRITE_2(sc, VTE_MIER, 0);
1782 CSR_WRITE_2(sc, VTE_MECIER, 0);
1836 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1862 CSR_WRITE_2(sc, VTE_MCR0, mcr);
2026 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
2027 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
2028 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
2029 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
2032 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
2034 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
2036 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
2039 CSR_WRITE_2(sc, VTE_MCR0, mcr);