Searched refs:AL_REG_FIELD_SET (Results 1 - 7 of 7) sorted by relevance
| /freebsd-12-stable/sys/contrib/alpine-hal/eth/ |
| H A D | al_hal_eth_kr.c | 377 AL_REG_FIELD_SET(cfg_lane_0,
381 AL_REG_FIELD_SET(cfg_lane_0,
391 AL_REG_FIELD_SET(cfg_lane_0,
395 AL_REG_FIELD_SET(cfg_lane_0,
405 AL_REG_FIELD_SET(cfg_lane_0,
409 AL_REG_FIELD_SET(cfg_lane_0,
415 AL_REG_FIELD_SET(cfg_lane_1,
419 AL_REG_FIELD_SET(cfg_lane_1,
425 AL_REG_FIELD_SET(cfg_lane_2,
429 AL_REG_FIELD_SET(cfg_lane_
[all...] |
| H A D | al_hal_eth_main.c | 1801 AL_REG_FIELD_SET(if_mode,
1806 AL_REG_FIELD_SET(if_mode,
1987 AL_REG_FIELD_SET(val, ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK,
2678 AL_REG_FIELD_SET(reg, EC_RFW_HDR_SPLIT_DEF_LEN_MASK, EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT, header_len);
2856 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, entry->prio_sel);
2857 AL_REG_FIELD_SET(val, AL_FIELD_MASK(7,4), 4, entry->queue_sel_1);
2858 AL_REG_FIELD_SET(val, AL_FIELD_MASK(9,8), 8, entry->queue_sel_2);
2859 AL_REG_FIELD_SET(val, AL_FIELD_MASK(13,10), 10, entry->udma_sel);
2860 AL_REG_FIELD_SET(val, AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel);
3049 AL_REG_FIELD_SET(va
[all...] |
| /freebsd-12-stable/sys/contrib/alpine-hal/ |
| H A D | al_hal_reg_utils.h | 69 #define AL_REG_FIELD_SET(reg, mask, shift, val) \ macro
89 AL_REG_FIELD_SET(reg, AL_BIT(shift), shift, val)
|
| H A D | al_hal_iofic.c | 77 AL_REG_FIELD_SET(reg,
99 AL_REG_FIELD_SET(reg,
122 AL_REG_FIELD_SET(reg,
143 AL_REG_FIELD_SET(reg,
|
| H A D | al_hal_serdes_hssp.c | 1545 AL_REG_FIELD_SET(reg,
1550 AL_REG_FIELD_SET(reg,
1562 AL_REG_FIELD_SET(reg,
1567 AL_REG_FIELD_SET(reg,
1579 AL_REG_FIELD_SET(reg,
1584 AL_REG_FIELD_SET(reg,
1665 AL_REG_FIELD_SET(reg,
1670 AL_REG_FIELD_SET(reg,
1682 AL_REG_FIELD_SET(reg,
1687 AL_REG_FIELD_SET(re
[all...] |
| H A D | al_hal_pcie.c | 393 AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit);
394 AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit);
587 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_LF_MASK,
590 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_FS_MASK,
597 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK,
600 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK,
947 AL_REG_FIELD_SET(reg, 0xF, 0, i);
1369 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
2296 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
2299 AL_REG_FIELD_SET(re
[all...] |
| H A D | al_hal_udma_config.c | 993 AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT, wait_for_desc_timeout);
|
Completed in 82 milliseconds