Lines Matching refs:AL_REG_FIELD_SET
393 AL_REG_FIELD_SET(reg, 0xFFFF, 0, lat_rply_timers->round_trip_lat_limit);
394 AL_REG_FIELD_SET(reg, 0xFFFF0000, 16, lat_rply_timers->replay_timer_limit);
587 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_LF_MASK,
590 AL_REG_FIELD_SET(reg, PCIE_PORT_GEN3_EQ_FS_MASK,
597 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK,
600 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK,
947 AL_REG_FIELD_SET(reg, 0xF, 0, i);
1369 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK,
2296 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK,
2299 AL_REG_FIELD_SET(reg, PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK,
2433 AL_REG_FIELD_SET(reg, 0xF, 0, atu_region->index);
2527 AL_REG_FIELD_SET(reg, 0x1F, 0, atu_region->tlp_type);
2528 AL_REG_FIELD_SET(reg, 0x3 << 9, 9, atu_region->attr);
2534 AL_REG_FIELD_SET(reg,
2544 AL_REG_FIELD_SET(reg, 0xFF, 0, atu_region->msg_code);
2545 AL_REG_FIELD_SET(reg, 0x700, 8, atu_region->bar_number);
2546 AL_REG_FIELD_SET(reg, 0x3 << 24, 24, atu_region->response);
2560 AL_REG_FIELD_SET(reg,
2581 AL_REG_FIELD_SET(reg, 0xF, 0, index);
2671 AL_REG_FIELD_SET(reg,