Lines Matching refs:AL_REG_FIELD_SET
1801 AL_REG_FIELD_SET(if_mode,
1806 AL_REG_FIELD_SET(if_mode,
1987 AL_REG_FIELD_SET(val, ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK,
2678 AL_REG_FIELD_SET(reg, EC_RFW_HDR_SPLIT_DEF_LEN_MASK, EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT, header_len);
2856 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, entry->prio_sel);
2857 AL_REG_FIELD_SET(val, AL_FIELD_MASK(7,4), 4, entry->queue_sel_1);
2858 AL_REG_FIELD_SET(val, AL_FIELD_MASK(9,8), 8, entry->queue_sel_2);
2859 AL_REG_FIELD_SET(val, AL_FIELD_MASK(13,10), 10, entry->udma_sel);
2860 AL_REG_FIELD_SET(val, AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel);
3049 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, udma_mask);
3050 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,4), 4, qid);
3061 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,2), 2, entry->udma_mask);
3262 AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_UDMA_MASK, EC_RFW_DEFAULT_OR_UDMA_SHIFT, params->udma);
3263 AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_QUEUE_MASK, EC_RFW_DEFAULT_OR_QUEUE_SHIFT, params->qid);
3642 AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
3679 AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
3683 AL_REG_FIELD_SET(reg, EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK,
3790 AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK,
3793 AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK,
3945 AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_SEL_MASK,
3948 AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK,
3952 AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK,
4437 AL_REG_FIELD_SET(reg, AL_HAL_ETH_MEDIA_TYPE_MASK,
4440 AL_REG_FIELD_SET(reg, AL_HAL_ETH_PHY_ADDR_MASK,
4448 AL_REG_FIELD_SET(reg, AL_HAL_ETH_MDIO_FREQ_MASK,
4450 AL_REG_FIELD_SET(reg, AL_HAL_ETH_I2C_ADAPTER_ID_MASK,
4452 AL_REG_FIELD_SET(reg, AL_HAL_ETH_EXT_PHY_IF_MASK,
4458 AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_GRP_MASK,
4464 AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_LANE_MASK,
4467 AL_REG_FIELD_SET(reg, AL_HAL_ETH_REF_CLK_FREQ_MASK,
4485 AL_REG_FIELD_SET(reg, AL_HAL_ETH_1G_SPEED_MASK,
4495 AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_BUS_ID_MASK,
4497 AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_I2C_ADDR_MASK,
4503 AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_CHANNEL_2_MASK,
4507 AL_REG_FIELD_SET(reg, AL_HAL_ETH_DAC_LENGTH_MASK,
4511 AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_TYPE_MASK,
4514 AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_TX_CHANNEL_MASK,
4523 AL_REG_FIELD_SET(reg, AL_HAL_ETH_GPIO_SFP_PRESENT_MASK,
4691 AL_REG_FIELD_SET(*reg, mask, (sizeof(uint8_t) * i), arr[i]);
4767 AL_REG_FIELD_SET(val, AL_ETH_TX_VLAN_TABLE_UDMA_MASK, 0, udma_mask);
4768 AL_REG_FIELD_SET(val, AL_ETH_TX_VLAN_TABLE_FWD_TO_MAC, 4, fwd_to_mac);