/freebsd-11.0-release/sys/mips/rmi/dev/xlr/ |
H A D | xgmac_mdio.h | 61 _mmio[0x10] = (0x0 << 3) | 0x5; 62 _mmio[0x10] = (0x1 << 3) | 0x5; 63 _mmio[0x10] = (0x0 << 3) | 0x5; 89 _mmio[0x10] = (0x0 << 3) | 0x5; 90 _mmio[0x10] = (0x1 << 3) | 0x5; 91 _mmio[0x10] = (0x0 << 3) | 0x5; 117 _mmio[0x10] = (0x0 << 3) | 0x5; 118 _mmio[0x10] = (0x1 << 3) | 0x5; 119 _mmio[0x10] = (0x0 << 3) | 0x5;
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/freebsd-11.0-release/contrib/pnpinfo/ |
H A D | pnpinfo.h | 58 #define DMA_FORMAT 0x5 72 #define _32BIT_MEM_RANGE_DESC 0x5
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/freebsd-11.0-release/sys/gnu/dts/arm/ |
H A D | imx6dl-pinfunc.h | 22 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 29 #define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 35 #define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 41 #define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 47 #define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 53 #define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 59 #define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 65 #define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 71 #define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 77 #define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 [all...] |
H A D | imx6q-pinfunc.h | 22 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 28 #define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 33 #define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 38 #define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 42 #define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 45 #define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 48 #define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 51 #define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 54 #define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 57 #define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 [all...] |
H A D | imx7d-pinfunc.h | 33 #define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 40 #define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 52 #define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 60 #define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 65 #define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 67 #define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 83 #define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 92 #define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 101 #define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 109 #define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 [all...] |
H A D | imx35-pinfunc.h | 22 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 27 #define MX35_PAD_COMPARE__GPIO1_5 0x008 0x32c 0x854 0x5 0x0 31 #define MX35_PAD_WDOG_RST__GPIO1_6 0x00c 0x330 0x858 0x5 0x0 48 #define MX35_PAD_CLKO__GPIO1_8 0x020 0x34c 0x860 0x5 0x0 55 #define MX35_PAD_VSTBY__GPIO1_7 0x024 0x364 0x85c 0x5 0x0 132 #define MX35_PAD_CS4__GPIO1_20 0x0b0 0x488 0x83c 0x5 0x0 137 #define MX35_PAD_CS5__GPIO1_21 0x0b4 0x48c 0x840 0x5 0x0 139 #define MX35_PAD_NF_CE0__GPIO1_22 0x0b8 0x490 0x844 0x5 0x0 157 #define MX35_PAD_NFWE_B__GPIO2_18 0x0c8 0x4cc 0x88c 0x5 0x0 162 #define MX35_PAD_NFRE_B__GPIO2_19 0x0cc 0x4d0 0x890 0x5 [all...] |
H A D | imx6sl-pinfunc.h | 22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 30 #define MX6SL_PAD_AUD_RXC__GPIO1_IO01 0x050 0x2a8 0x000 0x5 0x0 38 #define MX6SL_PAD_AUD_RXD__GPIO1_IO02 0x054 0x2ac 0x000 0x5 0x0 45 #define MX6SL_PAD_AUD_RXFS__GPIO1_IO00 0x058 0x2b0 0x000 0x5 0x0 53 #define MX6SL_PAD_AUD_TXC__GPIO1_IO03 0x05c 0x2b4 0x000 0x5 0x0 60 #define MX6SL_PAD_AUD_TXD__GPIO1_IO05 0x060 0x2b8 0x000 0x5 0x0 67 #define MX6SL_PAD_AUD_TXFS__GPIO1_IO04 0x064 0x2bc 0x000 0x5 0x0 74 #define MX6SL_PAD_ECSPI1_MISO__GPIO4_IO10 0x068 0x358 0x000 0x5 0x0 81 #define MX6SL_PAD_ECSPI1_MOSI__GPIO4_IO09 0x06c 0x35c 0x000 0x5 0x0 88 #define MX6SL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x070 0x360 0x000 0x5 [all...] |
H A D | imx6sx-pinfunc.h | 22 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 30 #define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0 38 #define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0 46 #define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0 55 #define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0 64 #define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0 73 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 82 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 91 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 100 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 [all...] |
H A D | imx53-pinfunc.h | 22 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 29 #define MX53_PAD_KEY_COL0__ECSPI1_SCLK 0x024 0x34c 0x79c 0x5 0x0 36 #define MX53_PAD_KEY_ROW0__ECSPI1_MOSI 0x028 0x350 0x7a4 0x5 0x0 42 #define MX53_PAD_KEY_COL1__ECSPI1_MISO 0x02c 0x354 0x7a0 0x5 0x0 49 #define MX53_PAD_KEY_ROW1__ECSPI1_SS0 0x030 0x358 0x7a8 0x5 0x0 56 #define MX53_PAD_KEY_COL2__ECSPI1_SS1 0x034 0x35c 0x7ac 0x5 0x0 63 #define MX53_PAD_KEY_ROW2__ECSPI1_SS2 0x038 0x360 0x7b0 0x5 0x0 71 #define MX53_PAD_KEY_COL3__ECSPI1_SS3 0x03c 0x364 0x7b4 0x5 0x0 79 #define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT 0x040 0x368 0x000 0x5 0x0 87 #define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC 0x044 0x36c 0x89c 0x5 [all...] |
H A D | imx51-pinfunc.h | 17 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 36 #define MX51_PAD_EIM_D19__AUD4_RXC 0x068 0x3fc 0x000 0x5 0x0 43 #define MX51_PAD_EIM_D20__AUD4_TXD 0x06c 0x400 0x8c8 0x5 0x0 48 #define MX51_PAD_EIM_D21__AUD4_RXD 0x070 0x404 0x8c4 0x5 0x0 53 #define MX51_PAD_EIM_D22__AUD4_TXC 0x074 0x408 0x8cc 0x5 0x0 57 #define MX51_PAD_EIM_D23__AUD4_TXFS 0x078 0x40c 0x8d0 0x5 0x0 62 #define MX51_PAD_EIM_D24__AUD6_RXFS 0x07c 0x410 0x8f8 0x5 0x0 78 #define MX51_PAD_EIM_D27__AUD6_RXC 0x088 0x41c 0x8f4 0x5 0x0 84 #define MX51_PAD_EIM_D28__AUD6_TXD 0x08c 0x420 0x8f0 0x5 0x0 88 #define MX51_PAD_EIM_D29__AUD6_RXD 0x090 0x424 0x8ec 0x5 [all...] |
/freebsd-11.0-release/sys/arm64/arm64/ |
H A D | bzero.S | 45 * x5 is number of cache lines to zero - calculated later and 49 * smaller than 16 bytes - otherwise the x5 will not be 52 * to cache line for buffers bigger than cache line; non-0 x5 55 * be performed, and x5 is amount of cache lines to loop through. 57 mov x5, xzr 80 * number of full cache lines (x5). x6 is final address to zero. 91 sub x5, x1, x4 94 lsr x5, x5, x2 100 cbz x5, norma [all...] |
H A D | swtch.S | 89 ldr x5, [x4, #PCB_L0ADDR] 90 msr ttbr0_el1, x5 104 ldp x5, x6, [x4, #PCB_SP] 105 mov sp, x5 151 mov x5, sp 153 stp x5, x6, [x4, #PCB_SP] 186 ldr x5, [x4, #PCB_L0ADDR] 187 msr ttbr0_el1, x5 215 ldp x5, x6, [x4, #PCB_SP] 216 mov sp, x5 [all...] |
/freebsd-11.0-release/crypto/openssl/engines/ccgost/ |
H A D | gost89.c | 51 {0x1, 0x3, 0xA, 0x9, 0x5, 0xB, 0x4, 0xF, 0x8, 0x6, 0x7, 0xE, 0xD, 0x0, 54 {0xD, 0xE, 0x4, 0x1, 0x7, 0x0, 0x5, 0xA, 0x3, 0xC, 0x8, 0xF, 0x6, 0x2, 57 {0x7, 0x6, 0x2, 0x4, 0xD, 0x9, 0xF, 0x0, 0xA, 0x1, 0x5, 0xB, 0x8, 0xE, 61 0x3, 0x5} 63 {0x4, 0xA, 0x7, 0xC, 0x0, 0xF, 0x2, 0x8, 0xE, 0x1, 0x6, 0x5, 0xD, 0xB, 66 {0x7, 0xF, 0xC, 0xE, 0x9, 0x4, 0x1, 0x0, 0x3, 0xB, 0x5, 0x2, 0x6, 0xA, 69 {0x5, 0xF, 0x4, 0x0, 0x2, 0xD, 0xB, 0x9, 0x1, 0x7, 0x6, 0x3, 0xC, 0xE, 72 {0xA, 0x4, 0x5, 0x6, 0x8, 0x1, 0x3, 0x7, 0xD, 0xC, 0xE, 0x0, 0x9, 0x2, 78 {0xC, 0x6, 0x5, 0x2, 0xB, 0x0, 0x9, 0xD, 0x3, 0xE, 0x7, 0xA, 0xF, 0x4, 81 {0x9, 0xB, 0xC, 0x0, 0x3, 0x6, 0x7, 0x5, [all...] |
/freebsd-11.0-release/crypto/heimdal/lib/wind/ |
H A D | bidi_table.c | 13 {0x5f0, 0x5}, 22 {0x6fa, 0x5}, 32 {0xfb38, 0x5}, 41 {0xfe70, 0x5}, 61 {0x2e0, 0x5}, 120 {0xab5, 0x5}, 164 {0xc35, 0x5}, 173 {0xcb5, 0x5}, 175 {0xcc0, 0x5}, 220 {0xec0, 0x5}, [all...] |
/freebsd-11.0-release/bin/sh/ |
H A D | parser.h | 60 #define VSASSIGN 0x5 /* ${var=text} */
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/freebsd-11.0-release/sys/mips/atheros/ |
H A D | pcf2123reg.h | 41 #define PCF2123_REG_DAYS 0x5
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/freebsd-11.0-release/sys/gnu/dts/include/dt-bindings/net/ |
H A D | ti-dp83867.h | 33 #define DP83867_RGMIIDCTL_1_50_NS 0x5
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/freebsd-11.0-release/sys/boot/i386/boot2/ |
H A D | sio.S | 58 movw $SIO_PRT+0x5,%dx # Line status reg 66 subb $0x5,%dl # Transmitter hold reg 74 sio_getc.1: subb $0x5,%dl # Receiver buffer reg 80 sio_ischar: movw $SIO_PRT+0x5,%dx # Line status register
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/freebsd-11.0-release/contrib/ntp/ntpdc/ |
H A D | ntpdc.h | 26 #define IP_VERSION 0x5 /* IP version */
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/freebsd-11.0-release/sys/dev/mc146818/ |
H A D | mc146818reg.h | 75 #define MC_AHOUR 0x5 /* Alarm: hour */ 129 #define MC_RATE_2048_Hz 0x5 /* 488.281 us period */
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/freebsd-11.0-release/sys/dev/ic/ |
H A D | via6522reg.h | 59 #define ACR_SRO_T2 0x5 /* Shift out under control of T2 */ 76 #define PCR_CNTL_PULSE 0x5 /* Pulse output */
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/freebsd-11.0-release/sys/gnu/dts/include/dt-bindings/pinctrl/ |
H A D | dra.h | 21 #define MUX_MODE5 0x5 39 #define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
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/freebsd-11.0-release/contrib/unbound/compat/ |
H A D | chacha_private.h | 91 u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15; local 128 x5 = j5; 141 QUARTERROUND( x1, x5, x9,x13) 144 QUARTERROUND( x0, x5,x10,x15) 154 x5 = PLUS(x5,j5); 172 x5 = XOR(x5,U8TO32_LITTLE(m + 20)); 196 U32TO8_LITTLE(c + 20,x5);
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/freebsd-11.0-release/crypto/openssh/ |
H A D | chacha.c | 92 u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15; local 129 x5 = j5; 142 QUARTERROUND( x1, x5, x9,x13) 145 QUARTERROUND( x0, x5,x10,x15) 155 x5 = PLUS(x5,j5); 172 x5 = XOR(x5,U8TO32_LITTLE(m + 20)); 195 U32TO8_LITTLE(c + 20,x5);
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/freebsd-11.0-release/crypto/openssh/openbsd-compat/ |
H A D | chacha_private.h | 91 u32 x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15; local 128 x5 = j5; 141 QUARTERROUND( x1, x5, x9,x13) 144 QUARTERROUND( x0, x5,x10,x15) 154 x5 = PLUS(x5,j5); 172 x5 = XOR(x5,U8TO32_LITTLE(m + 20)); 196 U32TO8_LITTLE(c + 20,x5);
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