1198157Srrs/*- 2198157Srrs * Copyright (c) 2003-2009 RMI Corporation 3198157Srrs * All rights reserved. 4198157Srrs * 5198157Srrs * Redistribution and use in source and binary forms, with or without 6198157Srrs * modification, are permitted provided that the following conditions 7198157Srrs * are met: 8198157Srrs * 1. Redistributions of source code must retain the above copyright 9198157Srrs * notice, this list of conditions and the following disclaimer. 10198157Srrs * 2. Redistributions in binary form must reproduce the above copyright 11198157Srrs * notice, this list of conditions and the following disclaimer in the 12198157Srrs * documentation and/or other materials provided with the distribution. 13198157Srrs * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14198157Srrs * may be used to endorse or promote products derived from this software 15198157Srrs * without specific prior written permission. 16198157Srrs * 17198157Srrs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18198157Srrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19198157Srrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20198157Srrs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21198157Srrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22198157Srrs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23198157Srrs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24198157Srrs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25198157Srrs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26198157Srrs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27198157Srrs * SUCH DAMAGE. 28198157Srrs * 29198157Srrs * RMI_BSD */ 30198157Srrs/* MDIO Low level Access routines */ 31198157Srrs/* All Phy's accessed from GMAC0 base */ 32198157Srrs 33198157Srrs#ifndef _XGMAC_MDIO_H_ 34198157Srrs#define _XGMAC_MDIO_H_ 35198157Srrs 36198157Srrsstatic inline int 37198157Srrsxmdio_read(volatile unsigned int *_mmio, 38198626Srrs uint32_t phy_addr, uint32_t address); 39198157Srrsstatic inline void 40198157Srrsxmdio_write(volatile unsigned int *_mmio, 41198626Srrs uint32_t phy_addr, uint32_t address, uint32_t data); 42198157Srrsstatic inline void 43198157Srrsxmdio_address(volatile unsigned int *_mmio, 44198626Srrs uint32_t phy_addr, uint32_t dev_ad, uint32_t address); 45198157Srrs 46198157Srrsstatic inline void 47198157Srrsxmdio_address(volatile unsigned int *_mmio, 48198626Srrs uint32_t phy_addr, uint32_t dev_ad, uint32_t address) 49198157Srrs{ 50198626Srrs uint32_t st_field = 0x0; 51198626Srrs uint32_t op_type = 0x0; /* address operation */ 52198626Srrs uint32_t ta_field = 0x2;/* ta field */ 53198157Srrs 54198157Srrs _mmio[0x11] = ((st_field & 0x3) << 30) | 55198626Srrs ((op_type & 0x3) << 28) | 56198626Srrs ((phy_addr & 0x1F) << 23) | 57198626Srrs ((dev_ad & 0x1F) << 18) | 58198626Srrs ((ta_field & 0x3) << 16) | 59198626Srrs ((address & 0xffff) << 0); 60198157Srrs 61198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 62198157Srrs _mmio[0x10] = (0x1 << 3) | 0x5; 63198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 64198157Srrs 65198157Srrs /* wait for dev_ad cycle to complete */ 66198157Srrs while (_mmio[0x14] & 0x1) { 67198157Srrs }; 68198157Srrs 69198157Srrs} 70198157Srrs 71198157Srrs/* function prototypes */ 72198157Srrsstatic inline int 73198157Srrsxmdio_read(volatile unsigned int *_mmio, 74198626Srrs uint32_t phy_addr, uint32_t address) 75198157Srrs{ 76198626Srrs uint32_t st_field = 0x0; 77198626Srrs uint32_t op_type = 0x3; /* read operation */ 78198626Srrs uint32_t ta_field = 0x2;/* ta field */ 79198626Srrs uint32_t data = 0; 80198157Srrs 81198157Srrs xmdio_address(_mmio, phy_addr, 5, address); 82198157Srrs _mmio[0x11] = ((st_field & 0x3) << 30) | 83198626Srrs ((op_type & 0x3) << 28) | 84198626Srrs ((phy_addr & 0x1F) << 23) | 85198626Srrs ((5 & 0x1F) << 18) | 86198626Srrs ((ta_field & 0x3) << 16) | 87198626Srrs ((data & 0xffff) << 0); 88198157Srrs 89198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 90198157Srrs _mmio[0x10] = (0x1 << 3) | 0x5; 91198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 92198157Srrs 93198157Srrs /* wait for write cycle to complete */ 94198157Srrs while (_mmio[0x14] & 0x1) { 95198157Srrs }; 96198157Srrs 97198157Srrs data = _mmio[0x11] & 0xffff; 98198157Srrs return (data); 99198157Srrs} 100198157Srrs 101198157Srrsstatic inline void 102198157Srrsxmdio_write(volatile unsigned int *_mmio, 103198626Srrs uint32_t phy_addr, uint32_t address, uint32_t data) 104198157Srrs{ 105198626Srrs uint32_t st_field = 0x0; 106198626Srrs uint32_t op_type = 0x1; /* write operation */ 107198626Srrs uint32_t ta_field = 0x2;/* ta field */ 108198157Srrs 109198157Srrs xmdio_address(_mmio, phy_addr, 5, address); 110198157Srrs _mmio[0x11] = ((st_field & 0x3) << 30) | 111198626Srrs ((op_type & 0x3) << 28) | 112198626Srrs ((phy_addr & 0x1F) << 23) | 113198626Srrs ((5 & 0x1F) << 18) | 114198626Srrs ((ta_field & 0x3) << 16) | 115198626Srrs ((data & 0xffff) << 0); 116198157Srrs 117198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 118198157Srrs _mmio[0x10] = (0x1 << 3) | 0x5; 119198157Srrs _mmio[0x10] = (0x0 << 3) | 0x5; 120198157Srrs 121198157Srrs /* wait for write cycle to complete */ 122198157Srrs while (_mmio[0x14] & 0x1) { 123198157Srrs }; 124198157Srrs 125198157Srrs} 126198157Srrs 127198157Srrs#endif 128