1153030Sgrehan/* 2153030Sgrehan * Copyright 2004 by Peter Grehan. All rights reserved. 3153030Sgrehan * 4153030Sgrehan * Redistribution and use in source and binary forms, with or without 5153030Sgrehan * modification, are permitted provided that the following conditions 6153030Sgrehan * are met: 7153030Sgrehan * 1. Redistributions of source code must retain the above copyright 8153030Sgrehan * notice, this list of conditions and the following disclaimer. 9153030Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 10153030Sgrehan * notice, this list of conditions and the following disclaimer in the 11153030Sgrehan * documentation and/or other materials provided with the distribution. 12153030Sgrehan * 3. The name of the author may not be used to endorse or promote products 13153030Sgrehan * derived from this software without specific prior written permission. 14153030Sgrehan * 15153030Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16153030Sgrehan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17153030Sgrehan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18153030Sgrehan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19153030Sgrehan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20153030Sgrehan * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21153030Sgrehan * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22153030Sgrehan * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23153030Sgrehan * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24153030Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25153030Sgrehan * SUCH DAMAGE. 26153030Sgrehan * 27153030Sgrehan * $FreeBSD: releng/11.0/sys/dev/ic/via6522reg.h 153030 2005-12-02 22:36:14Z grehan $ 28153030Sgrehan */ 29153030Sgrehan 30153030Sgrehan#ifndef _VIA6522REG_H_ 31153030Sgrehan#define _VIA6522REG_H_ 32153030Sgrehan 33153030Sgrehan/* Registers */ 34153030Sgrehan#define REG_OIRB 0 /* Input/output register B */ 35153030Sgrehan#define REG_OIRA 1 /* Input/output register A */ 36153030Sgrehan#define REG_DDRB 2 /* Data direction register B */ 37153030Sgrehan#define REG_DDRA 3 /* Data direction register A */ 38153030Sgrehan#define REG_T1CL 4 /* T1 low-order latch/low-order counter */ 39153030Sgrehan#define REG_T1CH 5 /* T1 high-order counter */ 40153030Sgrehan#define REG_T1LL 6 /* T1 low-order latches */ 41153030Sgrehan#define REG_T1LH 7 /* T1 high-order latches */ 42153030Sgrehan#define REG_T2CL 8 /* T2 low-order latch/low-order counter */ 43153030Sgrehan#define REG_T2CH 9 /* T2 high-order counter */ 44153030Sgrehan#define REG_SR 10 /* Shift register */ 45153030Sgrehan#define REG_ACR 11 /* Auxiliary control register */ 46153030Sgrehan#define REG_PCR 12 /* Peripheral control register */ 47153030Sgrehan#define REG_IFR 13 /* Interrupt flag register */ 48153030Sgrehan#define REG_IER 14 /* Interrupt-enable register */ 49153030Sgrehan#define REG_OIRA_NH 15 /* Input/output register A: no handshake */ 50153030Sgrehan 51153030Sgrehan 52153030Sgrehan/* Auxiliary control register (11) */ 53153030Sgrehan#define ACR_SR_NONE 0x0 /* Disabled */ 54153030Sgrehan#define ACR_SR_DIR 0x4 /* Bit for shift-register direction 1=out */ 55153030Sgrehan#define ACR_SRI_T2 0x1 /* Shift in under control of T2 */ 56153030Sgrehan#define ACR_SRI_PHI2 0x2 /* " " " " " PHI2 */ 57153030Sgrehan#define ACR_SRI_EXTCLK 0x3 /* " " " " " external clk */ 58153030Sgrehan#define ACR_SRO 0x4 /* Shift out free running at T2 rate */ 59153030Sgrehan#define ACR_SRO_T2 0x5 /* Shift out under control of T2 */ 60153030Sgrehan#define ACR_SRO_PHI2 0x6 /* " " " " " PHI2 */ 61153030Sgrehan#define ACR_SRO_EXTCLK 0x7 /* " " " " " external clk */ 62153030Sgrehan 63153030Sgrehan#define ACR_T1_SHIFT 5 /* bits 7-5 */ 64153030Sgrehan#define ACR_SR_SHIFT 2 /* bits 4-2 */ 65153030Sgrehan 66153030Sgrehan 67153030Sgrehan/* Peripheral control register (12) */ 68153030Sgrehan#define PCR_INTCNTL 0x01 /* interrupt active edge: +ve=1, -ve=0 */ 69153030Sgrehan 70153030Sgrehan#define PCR_CNTL_MASK 0x3 /* 3 bits */ 71153030Sgrehan#define PCR_CNTL_NEDGE 0x0 /* Input - negative active edge */ 72153030Sgrehan#define PCR_CNTL_INEDGE 0x1 /* Interrupt - negative active edge */ 73153030Sgrehan#define PCR_CNTL_PEDGE 0x2 /* Input - positive active edge */ 74153030Sgrehan#define PCR_CNTL_IPEDGE 0x3 /* Interrupt - positive active edge */ 75153030Sgrehan#define PCR_CNTL_HSHAKE 0x4 /* Handshake output */ 76153030Sgrehan#define PCR_CNTL_PULSE 0x5 /* Pulse output */ 77153030Sgrehan#define PCR_CNTL_LOW 0x6 /* Low output */ 78153030Sgrehan#define PCR_CNTL_HIGH 0x7 /* High output */ 79153030Sgrehan 80153030Sgrehan#define PCR_CB2_SHIFT 5 /* bits 7-5 */ 81153030Sgrehan#define PCR_CB1_SHIFT 4 /* bit 4 */ 82153030Sgrehan#define PCR_CA2_SHIFT 1 /* bits 3-1 */ 83153030Sgrehan#define PCR_CA1_SHIFT 0 /* bit 0 */ 84153030Sgrehan 85153030Sgrehan/* Interrupt flag register (13) */ 86153030Sgrehan#define IFR_CA2 0x01 87153030Sgrehan#define IFR_CA1 0x02 88153030Sgrehan#define IFR_SR 0x04 89153030Sgrehan#define IFR_CB2 0x08 90153030Sgrehan#define IFR_CB1 0x10 91153030Sgrehan#define IFR_T2 0x20 92153030Sgrehan#define IFR_T1 0x40 93153030Sgrehan#define IFR_IRQB 0x80 /* status of IRQB output pin */ 94153030Sgrehan 95153030Sgrehan/* Interrupt enable register (14) */ 96153030Sgrehan#define IER_CA2 IFR_CA2 97153030Sgrehan#define IER_CA1 IFR_CA1 98153030Sgrehan#define IER_SR IFR_SR 99153030Sgrehan#define IER_CB2 IFR_CB2 100153030Sgrehan#define IER_CB1 IFR_CB1 101153030Sgrehan#define IER_T2 IFR_T2 102153030Sgrehan#define IER_T1 IFR_T1 103153030Sgrehan#define IER_IRQB IFR_IRQB 104153030Sgrehan 105153030Sgrehan#endif /* _VIA6522REG_H_ */ 106