Searched refs:vBIT (Results 1 - 22 of 22) sorted by relevance

/freebsd-11.0-release/sys/dev/vxge/vxgehal/
H A Dvxgehal-mrpcim-reg.h54 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY_RPATH(val) vBIT(val, 5, 3)
55 #define VXGE_HAL_G3FBCT_CONFIG0_RD_CMD_LATENCY(val) vBIT(val, 13, 3)
56 #define VXGE_HAL_G3FBCT_CONFIG0_REFRESH_PER(val) vBIT(val, 16, 16)
57 #define VXGE_HAL_G3FBCT_CONFIG0_TRC(val) vBIT(val, 35, 5)
58 #define VXGE_HAL_G3FBCT_CONFIG0_TRRD(val) vBIT(val, 44, 4)
59 #define VXGE_HAL_G3FBCT_CONFIG0_TFAW(val) vBIT(val, 50, 6)
60 #define VXGE_HAL_G3FBCT_CONFIG0_RD_FIFO_THR(val) vBIT(val, 58, 6)
62 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_THR(val) vBIT(val, 3, 5)
65 #define VXGE_HAL_G3FBCT_CONFIG1_RD_SAMPLING(val) vBIT(val, 29, 3)
67 #define VXGE_HAL_G3FBCT_CONFIG1_BIC_HI_THR(val) vBIT(va
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H A Dvxgehal-legacy-reg.h43 #define VXGE_HAL_TOC_SWAPPER_FB_INITIAL_VAL(val) vBIT(val, 0, 64)
45 #define VXGE_HAL_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN(val) vBIT(val, 0, 64)
47 #define VXGE_HAL_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN(val) vBIT(val, 0, 64)
49 #define VXGE_HAL_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN(val) vBIT(val, 0, 64)
51 #define VXGE_HAL_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN(val) vBIT(val, 0, 64)
53 #define VXGE_HAL_TOC_FIRST_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
55 #define VXGE_HAL_HOST_ACCESS_EN_HOST_ACCESS_EN(val) vBIT(val, 0, 64)
H A Dvxgehal-toc-reg.h43 #define VXGE_HAL_TOC_COMMON_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
45 #define VXGE_HAL_TOC_MEMREPAIR_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
47 #define VXGE_HAL_TOC_PCICFGMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
51 #define VXGE_HAL_TOC_MRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
53 #define VXGE_HAL_TOC_SRPCIM_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
57 #define VXGE_HAL_TOC_VPMGMT_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
61 #define VXGE_HAL_TOC_VPATH_POINTER_INITIAL_VAL(val) vBIT(val, 0, 64)
65 #define VXGE_HAL_TOC_KDFC_INITIAL_OFFSET(val) vBIT(val, 0, 61)
66 #define VXGE_HAL_TOC_KDFC_INITIAL_BIR(val) vBIT(val, 61, 3)
68 #define VXGE_HAL_TOC_USDC_INITIAL_OFFSET(val) vBIT(va
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H A Dvxgehal-pcicfgmgmt-reg.h44 vBIT(val, 2, 6)
47 vBIT(val, 2, 6)
50 vBIT(val, 2, 6)
52 #define VXGE_HAL_MSIXGRP_NO_TABLE_SIZE(val) vBIT(val, 5, 11)
H A Dvxgehal-vpmgmt-reg.h43 #define VXGE_HAL_SGRP_OWN_SGRP_OWN(val) vBIT(val, 0, 64)
48 vBIT(val, 3, 5)
53 vBIT(val, 0, 64)
59 #define VXGE_HAL_TIM_VPATH_ASSIGNMENT_BMAP_ROOT(val) vBIT(val, 0, 32)
63 #define VXGE_HAL_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP(val) vBIT(val, 59, 5)
67 #define VXGE_HAL_USDC_VPATH_OWN_SGRP_OWN(val) vBIT(val, 0, 32)
95 vBIT(val, 24, 8)
105 vBIT(val, 5, 3)
107 vBIT(val, 9, 3)
109 vBIT(va
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H A Dvxgehal-vpath-reg.h43 #define VXGE_HAL_USDC_VPATH_SGRP_ASSIGN(val) vBIT(val, 0, 32)
59 #define VXGE_HAL_PRC_CFG1_RX_TIMER_VAL(val) vBIT(val, 3, 29)
65 #define VXGE_HAL_PRC_CFG1_RESET_TIMER_ON_RXD_RET(val) vBIT(val, 40, 2)
70 #define VXGE_HAL_PRC_CFG4_RING_MODE(val) vBIT(val, 14, 2)
77 #define VXGE_HAL_PRC_CFG4_BACKOFF_INTERVAL(val) vBIT(val, 40, 24)
79 #define VXGE_HAL_PRC_CFG5_RXD0_ADD(val) vBIT(val, 0, 61)
86 #define VXGE_HAL_PRC_CFG6_RXD_CRXDT(val) vBIT(val, 23, 9)
87 #define VXGE_HAL_PRC_CFG6_RXD_SPAT(val) vBIT(val, 36, 9)
89 #define VXGE_HAL_PRC_CFG7_SCATTER_MODE(val) vBIT(val, 6, 2)
93 #define VXGE_HAL_PRC_CFG7_RXD_BUFF_SIZE_MASK(val) vBIT(va
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H A Dvxgehal-common-reg.h83 #define VXGE_HAL_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE(val) vBIT(val, 0, 17)
95 #define VXGE_HAL_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(val) vBIT(val, 0, 17)
97 #define VXGE_HAL_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(val) vBIT(val, 0, 17)
99 #define VXGE_HAL_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0(val) vBIT(val, 0, 17)
101 #define VXGE_HAL_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1(val) vBIT(val, 0, 17)
103 #define VXGE_HAL_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2(val) vBIT(val, 0, 17)
107 #define VXGE_HAL_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM(val) vBIT(val, 0, 17)
109 #define VXGE_HAL_STATS_CFG0_STATS_ENABLE(val) vBIT(val, 0, 17)
113 #define VXGE_HAL_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT(val) vBIT(val, 0, 17)
115 #define VXGE_HAL_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT(val) vBIT(va
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H A Dvxgehal-doorbells.h56 #define VXGE_HAL_NODBW_TYPE(val) vBIT(val, 0, 8)
60 #define VXGE_HAL_NODBW_LAST_TXD_NUMBER(val) vBIT(val, 32, 8)
63 #define VXGE_HAL_NODBW_LIST_NO_SNOOP(val) vBIT(val, 56, 8)
97 #define VXGE_HAL_ODBW_TYPE(val) vBIT(val, 0, 8)
101 #define VXGE_HAL_ODBW_SESSION_NUMBER(val) vBIT(val, 8, 24)
104 #define VXGE_HAL_ODBW_SESSION_INST_NUMBER(val) vBIT(val, 32, 8)
107 #define VXGE_HAL_ODBW_HIGH_TOWI_NUMBER(val) vBIT(val, 40, 24)
111 #define VXGE_HAL_ODBW_ENTRY_TYPE(val) vBIT(val, 0, 8)
117 #define VXGE_HAL_ODBW_IMMEDIATE_BYTE_COUNT(val) vBIT(val, 8, 8)
146 #define VXGE_HAL_ODBW_TYPE(val) vBIT(va
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H A Dvxgehal-srpcim-reg.h42 vBIT(val, 0, 32)
78 #define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR0(val) vBIT(val, 11, 5)
79 #define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR1(val) vBIT(val, 19, 5)
80 #define VXGE_HAL_VF_BARGRP_NO_IDENTIFIER_LSB_FOR_BAR2(val) vBIT(val, 26, 6)
81 #define VXGE_HAL_VF_BARGRP_NO_FIRST_VF_OFFSET(val) vBIT(val, 32, 4)
82 #define VXGE_HAL_VF_BARGRP_NO_MASK(val) vBIT(val, 36, 4)
85 vBIT(val, 0, 64)
90 vBIT(val, 0, 64)
92 #define VXGE_HAL_VPATH_TO_SRPCIM_RMSG_SEL_SEL(val) vBIT(val, 0, 5)
95 vBIT(va
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H A Dvxgehal-regdefs.h119 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM(val) vBIT(val, 42, 5)
120 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM(val) vBIT(val, 47, 2)
121 #define VXGE_HAL_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET(val) vBIT(val, 49, 15)
152 #define VXGE_HAL_RTS_MGR_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
155 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK(val) vBIT(val, 0, 48)
159 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH(val) vBIT(val, 55, 5)
162 #define VXGE_HAL_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE(val) vBIT(val, 62, 2)
226 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(val) vBIT(val, 0, 48)
229 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_VLAN_ID(val) vBIT(val, 0, 12)
232 #define VXGE_HAL_RTS_ACCESS_STEER_DATA0_ETYPE(val) vBIT(va
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H A Dvxgehal-device.h166 vBIT(0x8, (i*4), 4); \
168 vBIT(0x4, (i*4), 4); \
170 vBIT(0x1, (i*4), 4); \
181 ~vBIT(0x8, (i*4), 4); \
183 ~vBIT(0x4, (i*4), 4); \
185 ~vBIT(0x1, (i*4), 4); \
H A Dvxgehal-virtualpath.c5168 val64 |= vBIT(0xf, (vp->vpath->vp_id * 4), 4);
5231 val64 &= ~(vBIT(0xf, (vp->vpath->vp_id * 4), 4));
6374 val64 |= vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6445 vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4),
6452 vBIT(VXGE_HAL_INTR_TX, 0, 4),
6509 val64 &= ~vBIT(VXGE_HAL_INTR_TX, (vpath->vp_id * 4), 4);
6582 val64 |= vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4);
6653 vBIT(VXGE_HAL_INTR_RX, (vpath->vp_id * 4), 4),
6660 (u32) bVAL32(vBIT(VXGE_HAL_INTR_RX, 0, 4), 0),
6715 val64 &= ~vBIT(VXGE_HAL_INTR_R
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H A Dvxgehal-mrpcim.c6552 vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS),
6557 vBIT(0xFFFFFFFFFFFFFFFFULL, 0, VXGE_HAL_MAX_VIRTUAL_PATHS),
/freebsd-11.0-release/sys/dev/nxge/include/
H A Dxgehal-regs.h66 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8)
67 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8)
68 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8)
69 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8)
93 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
94 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8)
95 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
97 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
107 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4)
126 #define XGE_HAL_PCI_INFO vBIT(
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H A Dxgehal-ring.h59 #define XGE_HAL_RXD_MASK_VLAN_TAG vBIT(0xFFFF,48,16)
71 #define XGE_HAL_RXD_MASK_FRAME_TYPE vBIT(0x3,25,2)
72 #define XGE_HAL_RXD_MASK_FRAME_PROTO vBIT(0xFFFF,24,8)
132 #define XGE_HAL_RXD_1_MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
133 #define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
135 (int)((Control_2 & vBIT(0xFFFF,0,16))>>48)
137 (u32)((Control_2 & vBIT(0xFFFFFFFF,16,32))>>16)
149 #define XGE_HAL_RXD_3_MASK_BUFFER0_SIZE vBIT(0xFF,8,8)
150 #define XGE_HAL_RXD_3_SET_BUFFER0_SIZE(val) vBIT(val,8,8)
151 #define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(
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H A Dxgehal-fifo.h62 #define XGE_HAL_TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
65 #define XGE_HAL_TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
67 #define XGE_HAL_TX_FIFO_NO_SNOOP(n) vBIT(n,30,2)
110 #define XGE_HAL_TXD_LSO_COF_CTRL(val) vBIT(val,30,2)
111 #define XGE_HAL_TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
112 #define XGE_HAL_TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
113 #define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
120 #define XGE_HAL_TXD_VLAN_TAG(val) vBIT(val,16,16)
121 #define XGE_HAL_TXD_INT_NUMBER(val) vBIT(val,34,6)
124 #define XGE_HAL_TXD_SET_MARKER vBIT(
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H A Dxgehal-types.h42 * vBIT(val, loc, sz) - set bits at offset
44 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) macro
/freebsd-11.0-release/sys/dev/vxge/include/
H A Dvxgehal-ll.h525 #define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7)
540 #define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4)
574 #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4)
596 #define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2)
618 #define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5)
628 #define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16)
631 #define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16)
637 #define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(val) vBIT(val, 2, 14)
638 #define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK vBIT(0x3FFF, 2, 14)
641 #define VXGE_HAL_RING_RXD_1_RTH_HASH_VAL(val) vBIT(va
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H A Dvxge-defs.h60 * vBIT(val, loc, sz) - set bits at offset
62 #define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) macro
/freebsd-11.0-release/sys/dev/nxge/xgehal/
H A Dxgehal-ring.c429 val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
498 val64 |= vBIT(hldev->config.ring.queue[i].priority,
511 val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
H A Dxgehal-fifo.c406 vBIT((hldev->config.fifo.queue[i].max-1),
408 13) | vBIT(priority, (((reg_half)*32) + 5), 3);
H A Dxgehal-device.c1565 val64 = vBIT(port->num,8,16) |
1566 vBIT(rnum,37,3) | BIT(63);
1575 val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8);
1947 spdm_line_arr[0] = vBIT(l4_sp,0,16) |
1948 vBIT(l4_dp,16,32) |
1949 vBIT(tgt_queue,53,3) |
1950 vBIT(is_tcp,59,1) |
1951 vBIT(is_ipv4,63,1);
1955 spdm_line_arr[1] = vBIT(src_ip->ipv4.addr,0,32) |
1956 vBIT(dst_i
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