Lines Matching refs:vBIT
66 #define XGE_HAL_SW_RESET_XENA vBIT(0xA5,0,8)
67 #define XGE_HAL_SW_RESET_FLASH vBIT(0xA5,8,8)
68 #define XGE_HAL_SW_RESET_EOI vBIT(0xA5,16,8)
69 #define XGE_HAL_SW_RESET_XGXS vBIT(0xA5,24,8)
93 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
94 #define XGE_HAL_ADAPTER_STATUS_RMAC_PCC_4_IDLE vBIT(0x0F,8,8)
95 #define XGE_HAL_ADAPTER_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
97 #define XGE_HAL_ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
107 #define XGE_HAL_ADAPTER_UDPI(val) vBIT(val,36,4)
126 #define XGE_HAL_PCI_INFO vBIT(0xF,0,4)
229 #define XGE_HAL_PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
263 #define XGE_HAL_SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6)
264 #define XGE_HAL_SCHED_INT_PERIOD(val) vBIT(val,32,32)
269 #define XGE_HAL_TXREQTO_VAL(val) vBIT(val,0,32)
284 #define XGE_HAL_XMSI_BYTE_COUNT(val) vBIT(val,13,3)
289 #define XGE_HAL_XMSI_NO(val) vBIT(val,26,6)
295 #define XGE_HAL_SET_RX_MAT(ring, msi) vBIT(msi, (8 * ring), 8)
300 #define XGE_HAL_SET_TX_MAT(fifo, msi) vBIT(msi, (8 * fifo), 8)
312 #define XGE_HAL_SET_UPDT_PERIOD(n) vBIT(n,32,32)
318 #define XGE_HAL_MDIO_CONTROL_MMD_INDX_ADDR(n) vBIT(n,0,16)
319 #define XGE_HAL_MDIO_CONTROL_MMD_DEV_ADDR(n) vBIT(n,19,5)
320 #define XGE_HAL_MDIO_CONTROL_MMD_PRT_ADDR(n) vBIT(n,27,5)
321 #define XGE_HAL_MDIO_CONTROL_MMD_DATA(n) vBIT(n,32,16)
322 #define XGE_HAL_MDIO_CONTROL_MMD_CTRL(n) vBIT(n,56,4)
323 #define XGE_HAL_MDIO_CONTROL_MMD_OP(n) vBIT(n,60,2)
350 #define XGE_HAL_I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
351 #define XGE_HAL_I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
352 #define XGE_HAL_I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
355 #define XGE_HAL_I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
356 #define XGE_HAL_I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
358 #define XGE_HAL_I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
362 #define XGE_HAL_MISC_CONTROL_LINK_STABILITY_PERIOD(val) vBIT(val,29,3)
374 #define XGE_HAL_TXD_WRITE_BC(n) vBIT(n, 13, 3)
450 #define XGE_HAL_TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8)
451 #define XGE_HAL_TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8)
459 #define XGE_HAL_PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8)
460 #define XGE_HAL_PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8)
461 #define XGE_HAL_PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8)
462 #define XGE_HAL_PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8)
463 #define XGE_HAL_PCC_SM_ERR_ALARM vBIT(0xff,32,8)
464 #define XGE_HAL_PCC_WR_ERR_ALARM vBIT(0xff,40,8)
465 #define XGE_HAL_PCC_N_SERR vBIT(0xff,48,8)
466 #define XGE_HAL_PCC_ENABLE_FOUR vBIT(0x0F,0,8)
512 #define XGE_HAL_TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
513 #define XGE_HAL_TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
514 #define XGE_HAL_TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
515 #define XGE_HAL_TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
518 #define XGE_HAL_TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
519 #define XGE_HAL_TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
520 #define XGE_HAL_TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
521 #define XGE_HAL_TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
524 #define XGE_HAL_TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
525 #define XGE_HAL_TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
526 #define XGE_HAL_TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
527 #define XGE_HAL_TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
530 #define XGE_HAL_TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
531 #define XGE_HAL_TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
532 #define XGE_HAL_TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
533 #define XGE_HAL_TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
554 #define XGE_HAL_TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
557 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
558 #define XGE_HAL_TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
561 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
562 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
563 #define XGE_HAL_TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
566 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
567 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
568 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
569 #define XGE_HAL_TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
609 #define XGE_HAL_RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8)
610 #define XGE_HAL_RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8)
622 #define XGE_HAL_RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8)
623 #define XGE_HAL_RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8)
626 #define XGE_HAL_RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8)
628 #define XGE_HAL_RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8)
633 #define XGE_HAL_PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8)
634 #define XGE_HAL_PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8)
635 #define XGE_HAL_PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8)
636 #define XGE_HAL_PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8)
637 #define XGE_HAL_PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8)
638 #define XGE_HAL_PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8)
662 #define XGE_HAL_RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
663 #define XGE_HAL_RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
664 #define XGE_HAL_RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
665 #define XGE_HAL_RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
666 #define XGE_HAL_RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
667 #define XGE_HAL_RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
668 #define XGE_HAL_RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
669 #define XGE_HAL_RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
692 #define XGE_HAL_PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
693 #define XGE_HAL_PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
694 #define XGE_HAL_PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
695 #define XGE_HAL_PRC_CTRL_RING_MODE_x vBIT(3,14,2)
696 #define XGE_HAL_PRC_CTRL_NO_SNOOP(n) vBIT(n,22,2)
700 #define XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
726 #define XGE_HAL_RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
729 #define XGE_HAL_RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
732 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
733 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
734 #define XGE_HAL_RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
737 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
738 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
739 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
740 #define XGE_HAL_RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
746 #define XGE_HAL_RX_PA_CFG_SCATTER_MODE(n) vBIT(n,6,1)
747 #define XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(n) vBIT(n,15,1)
800 #define XGE_HAL_MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
803 #define XGE_HAL_TMAC_AVG_IPG(val) vBIT(val,0,8)
806 #define XGE_HAL_RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
819 #define XGE_HAL_RMAC_CFG_KEY(val) vBIT(val,0,16)
831 #define XGE_HAL_RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
834 #define XGE_HAL_RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
838 #define XGE_HAL_RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
846 #define XGE_HAL_RMAC_ADDR_BCAST_EN vBIT(0)_48
847 #define XGE_HAL_RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
854 #define XGE_HAL_RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
855 #define XGE_HAL_RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
863 #define XGE_HAL_MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
864 #define XGE_HAL_MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
865 #define XGE_HAL_MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
866 #define XGE_HAL_MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
867 #define XGE_HAL_MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
868 #define XGE_HAL_MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
876 #define XGE_HAL_MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
883 #define XGE_HAL_RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
888 #define XGE_HAL_RTS_DEFAULT_Q(n) vBIT(n,5,3)
899 #define XGE_HAL_RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
902 #define XGE_HAL_RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
903 #define XGE_HAL_RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
909 #define XGE_HAL_RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
911 #define XGE_HAL_RTS_DS_MEM_DATA(n) vBIT(n,0,8)
936 #define XGE_HAL_RTS_RTH_BUCKET_SIZE(n) vBIT(n,4,4)
951 #define XGE_HAL_RTS_RTH_MAP_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
955 #define XGE_HAL_RTS_RTH_MAP_MEM_DATA(n) vBIT(n,5,3)
959 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_LINE_SEL(n) vBIT(n,21,3)
960 #define XGE_HAL_RTS_RTH_SPDM_MEM_CTRL_OFFSET(n) vBIT(n,24,8)
965 #define XGE_HAL_RTS_RTH_JHASH_GOLDEN(n) vBIT(n,0,32)
966 #define XGE_HAL_RTS_RTH_JHASH_INIT_VAL(n) vBIT(n,32,32)
970 #define XGE_HAL_RTH_HASH_MASK_5(n) vBIT(n,0,32)
1060 #define XGE_HAL_RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
1061 #define XGE_HAL_RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
1062 #define XGE_HAL_RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
1063 #define XGE_HAL_RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
1064 #define XGE_HAL_RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
1065 #define XGE_HAL_RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
1066 #define XGE_HAL_RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
1067 #define XGE_HAL_RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
1124 #define XGE_HAL_MC_RLDRAM_SET_REF_PERIOD(n) vBIT(n, 0, 16)
1127 #define XGE_HAL_MC_RLDRAM_MRS(n) vBIT(n, 14, 17)