vxge/include/vxgehal-ll.h

525 #define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER		    vBIT(val, 0, 7)
540 #define	VXGE_HAL_RING_RXD_T_CODE(val)			    vBIT(val, 12, 4)
574 #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)		    vBIT(val, 20, 4)
596 #define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)		    vBIT(val, 25, 2)
618 #define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)		    vBIT(val, 27, 5)
628 #define	VXGE_HAL_RING_RXD_L3_CKSUM(val)			    vBIT(val, 32, 16)
631 #define	VXGE_HAL_RING_RXD_L4_CKSUM(val)			    vBIT(val, 48, 16)
637 #define	VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
638 #define	VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK		    vBIT(0x3FFF, 2, 14)
641 #define	VXGE_HAL_RING_RXD_1_RTH_HASH_VAL(val)		    vBIT(val, 16, 32)
644 #define	VXGE_HAL_RING_RXD_VLAN_TAG(val)			    vBIT(val, 48, 16)
775  * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER	    vBIT(val, 0, 7)
793  * #define	VXGE_HAL_RING_RXD_T_CODE(val)		    vBIT(val, 12, 4)
831  * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)	    vBIT(val, 20, 4)
857  * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)	    vBIT(val, 25, 2)
879  * #define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)	    vBIT(val, 27, 5)
894  * #define	VXGE_HAL_RING_RXD_L3_CKSUM(val)		    vBIT(val, 32, 16)
897  * #define	VXGE_HAL_RING_RXD_L4_CKSUM(val)		    vBIT(val, 48, 16)
905 #define	VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
906 #define	VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK		    vBIT(0x3FFc, 2, 14)
909 #define	VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(val)		    vBIT(val, 18, 14)
910 #define	VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK		    vBIT(0x3FFc, 18, 14)
913 #define	VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(val)		    vBIT(val, 34, 14)
914 #define	VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK		    vBIT(0x3FFc, 34, 14)
920  * #define	VXGE_HAL_RING_RXD_VLAN_TAG(val)		    vBIT(val, 48, 16)
924 #define	VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE(val)		    vBIT(val, 32, 32)
1067 #define	VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(val)		    vBIT(val, 34, 14)
1068 #define	VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK		    vBIT(0x3FFF, 34, 14)
1071 #define	VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(val)		    vBIT(val, 50, 14)
1072 #define	VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK		    vBIT(0x3FFF, 50, 14)
1080  * #define	VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER	    vBIT(val, 0, 7)
1098  * #define	VXGE_HAL_RING_RXD_T_CODE(val)		    vBIT(val, 12, 4)
1139  * #define	VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val)	    vBIT(val, 20, 4)
1165  * #define	VXGE_HAL_RING_RXD_ETHER_ENCAP(val)	    vBIT(val, 25, 2)
1187  * #define	VXGE_HAL_RING_RXD_FRAME_PROTO(val)	    vBIT(val, 27, 5)
1198  * #define	VXGE_HAL_RING_RXD_L3_CKSUM(val)		    vBIT(val, 32, 16)
1201  * #define	VXGE_HAL_RING_RXD_L4_CKSUM(val)		    vBIT(val, 48, 16)
1207 #define	VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(val)		    vBIT(val, 2, 14)
1208 #define	VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK		    vBIT(0x3FFF, 2, 14)
1211 #define	VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(val)		    vBIT(val, 18, 14)
1212 #define	VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK		    vBIT(0x3FFF, 18, 14)
1215 #define	VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(val)		    vBIT(val, 34, 14)
1216 #define	VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK		    vBIT(0xFFFF, 34, 14)
1222  * #define	VXGE_HAL_RING_RXD_VLAN_TAG(val)		    vBIT(val, 48, 16)
1227 #define	VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE(val)		    vBIT(val, 32, 32)
2171 #define	VXGE_HAL_FIFO_TXD_T_CODE(val)			    vBIT(val, 12, 4)
2183 #define	VXGE_HAL_FIFO_TXD_HOST_STEER(val)		    vBIT(val, 16, 2)
2190 #define	VXGE_HAL_FIFO_TXD_GATHER_CODE(val)		    vBIT(val, 22, 2)
2198 #define	VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(val)		    vBIT(val, 28, 2)
2208 #define	VXGE_HAL_FIFO_TXD_LSO_MSS(val)			    vBIT(val, 34, 14)
2211 #define	VXGE_HAL_FIFO_TXD_BUFFER_SIZE(val)		    vBIT(val, 48, 16)
2214 #define	VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT(val)		    vBIT(val, 32, 32)
2232 #define	VXGE_HAL_FIFO_TXD_VLAN_TAG(val)			    vBIT(val, 16, 16)
2235 #define	VXGE_HAL_FIFO_TXD_INT_NUMBER(val)		    vBIT(val, 34, 6)