Searched refs:isUse (Results 1 - 25 of 69) sorted by relevance

123

/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DProcessImplicitDefs.cpp72 if (MO.isReg() && MO.isUse() && MO.readsReg())
112 if (MO.isUse())
H A DExpandPostRAPseudos.cpp74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
H A DRegAllocFast.cpp236 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
610 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
642 if (MO.isUse())
742 if (MO.isUse()) {
931 if (MO.isUse()) {
943 if (MO.isUse()) {
979 if (MO.isUse()) {
H A DMachineInstr.cpp349 if (isUndef() && isUse()) {
814 if (NewMO->isUse()) {
1150 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1234 if (!MO.isReg() || !MO.isUse())
1266 if (MO.isUse())
1346 assert(UseMO.isUse() && "UseIdx must be a use operand");
1378 if (MO.isUse())
1383 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1426 if (MO.isReg() && MO.isUse())
1590 if (!MO.isReg() || MO.isUse())
[all...]
H A DRegisterScavenging.cpp133 if (MO.isUse()) {
204 if (MO.isUse()) {
376 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
H A DDeadMachineInstructionElim.cpp159 if (MO.isReg() && MO.isUse()) {
H A DLivePhysRegs.cpp88 assert(O->isUse());
H A DMachineSink.cpp374 if (!MO.isReg() || !MO.isUse())
607 if (MO.isUse()) {
619 if (MO.isUse()) continue;
808 if (MO.isReg() && MO.isUse())
H A DTwoAddressInstructionPass.cpp207 if (MO.isUse() && MOReg != SavedReg)
367 if (MO.isUse() && DI->second < LastUse)
478 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
1057 if (MO.isUse()) {
1097 if (MO.isUse()) {
1347 if (MO.isUse()) {
1426 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1539 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1565 MO.isUse()) {
1601 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
[all...]
H A DCriticalAntiDepBreaker.cpp227 if (MO.isUse() && Special) {
291 if (!MO.isUse()) continue;
602 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
H A DMachineCSE.cpp126 if (!MO.isReg() || !MO.isUse())
195 if (MO.isUse())
397 if (MO.isReg() && MO.isUse() &&
H A DLiveIntervalAnalysis.cpp767 if (MO.isUse()) {
841 LiveIntervals::getSpillWeight(bool isDef, bool isUse, argument
846 return (isDef + isUse) * (Freq.getFrequency() * Scale);
967 if (MO.isUse())
1062 if (MO->isReg() && MO->isUse())
1359 } else if (MO.isUse()) {
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp265 if (MO.isUse()) {
290 assert(Reg.isUse() && "CALL first operand is not a use.");
297 assert(RegOrImm.isUse() && "CALLrr second operand is not a use.");
318 if (MO.isUse()) {
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DSIInsertWaits.cpp233 if (I->isReg() && I->isUse())
317 if (Op.isUse())
425 if (Op.isUse())
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp153 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
605 if (MO.isReg() && MO.isUse()) {
612 if (localMO.isReg() && localMO.isUse() &&
H A DHexagonGenPredicate.cpp240 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
336 if (Mo->isReg() && Mo->isUse())
358 if (!MO.isReg() || !MO.isUse())
H A DHexagonExpandCondsets.cpp277 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
366 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
514 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef())
631 if (!Op.isReg() || !Op.isUse())
1115 if (MO.isReg() && MO.isUse() && MO.isImplicit())
1142 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.isUndef()) {
H A DHexagonVLIWPacketizer.cpp283 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg))
461 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
682 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
827 if (Op.isReg() && Op.getReg() && Op.isUse() &&
1537 if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg)
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h767 if ((!ReturnUses && op->isUse()) ||
782 if (Op->isUse())
869 if ((!ReturnUses && op->isUse()) ||
884 if (Op->isUse())
H A DMachineOperand.h277 bool isUse() const { function in class:llvm::MachineOperand
336 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
H A DLiveIntervalAnalysis.h106 static float getSpillWeight(bool isDef, bool isUse,
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegColoring.cpp68 weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI,
H A DWebAssemblyRegStackify.cpp168 if (!Op.isReg() || Op.isImplicit() || !Op.isUse())
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp70 if (MO.isUse())
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp110 if (!MO.isReg() || !MO.isUse() ||

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