1//===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
11// instructions after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/raw_ostream.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Target/TargetSubtargetInfo.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE "postrapseudos"
29
30namespace {
31struct ExpandPostRA : public MachineFunctionPass {
32private:
33  const TargetRegisterInfo *TRI;
34  const TargetInstrInfo *TII;
35
36public:
37  static char ID; // Pass identification, replacement for typeid
38  ExpandPostRA() : MachineFunctionPass(ID) {}
39
40  void getAnalysisUsage(AnalysisUsage &AU) const override {
41    AU.setPreservesCFG();
42    AU.addPreservedID(MachineLoopInfoID);
43    AU.addPreservedID(MachineDominatorsID);
44    MachineFunctionPass::getAnalysisUsage(AU);
45  }
46
47  /// runOnMachineFunction - pass entry point
48  bool runOnMachineFunction(MachineFunction&) override;
49
50private:
51  bool LowerSubregToReg(MachineInstr *MI);
52  bool LowerCopy(MachineInstr *MI);
53
54  void TransferImplicitDefs(MachineInstr *MI);
55};
56} // end anonymous namespace
57
58char ExpandPostRA::ID = 0;
59char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
60
61INITIALIZE_PASS(ExpandPostRA, "postrapseudos",
62                "Post-RA pseudo instruction expansion pass", false, false)
63
64/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
65/// replacement instructions immediately precede it.  Copy any implicit-def
66/// operands from MI to the replacement instruction.
67void
68ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
69  MachineBasicBlock::iterator CopyMI = MI;
70  --CopyMI;
71
72  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
73    MachineOperand &MO = MI->getOperand(i);
74    if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
75      continue;
76    CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
77  }
78}
79
80bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
81  MachineBasicBlock *MBB = MI->getParent();
82  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
83         MI->getOperand(1).isImm() &&
84         (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
85          MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
86
87  unsigned DstReg  = MI->getOperand(0).getReg();
88  unsigned InsReg  = MI->getOperand(2).getReg();
89  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
90  unsigned SubIdx  = MI->getOperand(3).getImm();
91
92  assert(SubIdx != 0 && "Invalid index for insert_subreg");
93  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
94
95  assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
96         "Insert destination must be in a physical register");
97  assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
98         "Inserted value must be in a physical register");
99
100  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
101
102  if (MI->allDefsAreDead()) {
103    MI->setDesc(TII->get(TargetOpcode::KILL));
104    DEBUG(dbgs() << "subreg: replaced by: " << *MI);
105    return true;
106  }
107
108  if (DstSubReg == InsReg) {
109    // No need to insert an identity copy instruction.
110    // Watch out for case like this:
111    // %RAX<def> = SUBREG_TO_REG 0, %EAX<kill>, 3
112    // We must leave %RAX live.
113    if (DstReg != InsReg) {
114      MI->setDesc(TII->get(TargetOpcode::KILL));
115      MI->RemoveOperand(3);     // SubIdx
116      MI->RemoveOperand(1);     // Imm
117      DEBUG(dbgs() << "subreg: replace by: " << *MI);
118      return true;
119    }
120    DEBUG(dbgs() << "subreg: eliminated!");
121  } else {
122    TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
123                     MI->getOperand(2).isKill());
124
125    // Implicitly define DstReg for subsequent uses.
126    MachineBasicBlock::iterator CopyMI = MI;
127    --CopyMI;
128    CopyMI->addRegisterDefined(DstReg);
129    DEBUG(dbgs() << "subreg: " << *CopyMI);
130  }
131
132  DEBUG(dbgs() << '\n');
133  MBB->erase(MI);
134  return true;
135}
136
137bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
138
139  if (MI->allDefsAreDead()) {
140    DEBUG(dbgs() << "dead copy: " << *MI);
141    MI->setDesc(TII->get(TargetOpcode::KILL));
142    DEBUG(dbgs() << "replaced by: " << *MI);
143    return true;
144  }
145
146  MachineOperand &DstMO = MI->getOperand(0);
147  MachineOperand &SrcMO = MI->getOperand(1);
148
149  if (SrcMO.getReg() == DstMO.getReg()) {
150    DEBUG(dbgs() << "identity copy: " << *MI);
151    // No need to insert an identity copy instruction, but replace with a KILL
152    // if liveness is changed.
153    if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
154      // We must make sure the super-register gets killed. Replace the
155      // instruction with KILL.
156      MI->setDesc(TII->get(TargetOpcode::KILL));
157      DEBUG(dbgs() << "replaced by:   " << *MI);
158      return true;
159    }
160    // Vanilla identity copy.
161    MI->eraseFromParent();
162    return true;
163  }
164
165  DEBUG(dbgs() << "real copy:   " << *MI);
166  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
167                   DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
168
169  if (MI->getNumOperands() > 2)
170    TransferImplicitDefs(MI);
171  DEBUG({
172    MachineBasicBlock::iterator dMI = MI;
173    dbgs() << "replaced by: " << *(--dMI);
174  });
175  MI->eraseFromParent();
176  return true;
177}
178
179/// runOnMachineFunction - Reduce subregister inserts and extracts to register
180/// copies.
181///
182bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
183  DEBUG(dbgs() << "Machine Function\n"
184               << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
185               << "********** Function: " << MF.getName() << '\n');
186  TRI = MF.getSubtarget().getRegisterInfo();
187  TII = MF.getSubtarget().getInstrInfo();
188
189  bool MadeChange = false;
190
191  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
192       mbbi != mbbe; ++mbbi) {
193    for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
194         mi != me;) {
195      MachineInstr *MI = mi;
196      // Advance iterator here because MI may be erased.
197      ++mi;
198
199      // Only expand pseudos.
200      if (!MI->isPseudo())
201        continue;
202
203      // Give targets a chance to expand even standard pseudos.
204      if (TII->expandPostRAPseudo(MI)) {
205        MadeChange = true;
206        continue;
207      }
208
209      // Expand standard pseudos.
210      switch (MI->getOpcode()) {
211      case TargetOpcode::SUBREG_TO_REG:
212        MadeChange |= LowerSubregToReg(MI);
213        break;
214      case TargetOpcode::COPY:
215        MadeChange |= LowerCopy(MI);
216        break;
217      case TargetOpcode::DBG_VALUE:
218        continue;
219      case TargetOpcode::INSERT_SUBREG:
220      case TargetOpcode::EXTRACT_SUBREG:
221        llvm_unreachable("Sub-register pseudos should have been eliminated.");
222      }
223    }
224  }
225
226  return MadeChange;
227}
228