Searched refs:hasV6Ops (Results 1 - 9 of 9) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMSubtarget.h308 bool hasV6Ops() const { return HasV6Ops; } function in class:llvm::ARMSubtarget
347 return HasDataBarrier || (hasV6Ops() && !isThumb());
H A DThumb1InstrInfo.cpp51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
H A DARMSubtarget.cpp359 if (!hasV6Ops())
H A DARMLoadStoreOptimizer.cpp685 !STI->hasV6Ops()) {
2030 unsigned ReqAlign = STI->hasV6Ops()
H A DARMISelDAGToDAG.cpp2672 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2688 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2704 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2720 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
H A DARMFastISel.cpp2604 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops
2675 bool hasV6Ops = Subtarget->hasV6Ops(); local
2679 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
H A DARMAsmPrinter.cpp573 else if (Subtarget->hasV6Ops())
H A DARMISelLowering.cpp729 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
773 if (!Subtarget->hasV6Ops())
880 if (!Subtarget->hasV6Ops()) {
1018 if (Subtarget->hasV6Ops())
1266 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
2953 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
10372 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
11296 if (!Subtarget->hasV6Ops())
11929 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp260 bool hasV6Ops() const { function in class:__anon2786::ARMAsmParser
8546 else if (Opc == ARM::tMOVr && !hasV6Ops() &&

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