1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
16
17
18#include "ARMFrameLowering.h"
19#include "ARMISelLowering.h"
20#include "ARMInstrInfo.h"
21#include "ARMSelectionDAGInfo.h"
22#include "ARMSubtarget.h"
23#include "MCTargetDesc/ARMMCTargetDesc.h"
24#include "Thumb1FrameLowering.h"
25#include "Thumb1InstrInfo.h"
26#include "Thumb2InstrInfo.h"
27#include "llvm/ADT/Triple.h"
28#include "llvm/IR/DataLayout.h"
29#include "llvm/MC/MCInstrItineraries.h"
30#include "llvm/Target/TargetSubtargetInfo.h"
31#include <string>
32
33#define GET_SUBTARGETINFO_HEADER
34#include "ARMGenSubtargetInfo.inc"
35
36namespace llvm {
37class GlobalValue;
38class StringRef;
39class TargetOptions;
40class ARMBaseTargetMachine;
41
42class ARMSubtarget : public ARMGenSubtargetInfo {
43protected:
44  enum ARMProcFamilyEnum {
45    Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
46    CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA35, CortexA53,
47    CortexA57, CortexA72, Krait, Swift, ExynosM1
48  };
49  enum ARMProcClassEnum {
50    None, AClass, RClass, MClass
51  };
52  enum ARMArchEnum {
53    ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
54    ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
55    ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a
56  };
57
58  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
59  ARMProcFamilyEnum ARMProcFamily;
60
61  /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
62  ARMProcClassEnum ARMProcClass;
63
64  /// ARMArch - ARM architecture
65  ARMArchEnum ARMArch;
66
67  /// HasV4TOps, HasV5TOps, HasV5TEOps,
68  /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
69  /// Specify whether target support specific ARM ISA variants.
70  bool HasV4TOps;
71  bool HasV5TOps;
72  bool HasV5TEOps;
73  bool HasV6Ops;
74  bool HasV6MOps;
75  bool HasV6KOps;
76  bool HasV6T2Ops;
77  bool HasV7Ops;
78  bool HasV8Ops;
79  bool HasV8_1aOps;
80  bool HasV8_2aOps;
81
82  /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
83  /// floating point ISAs are supported.
84  bool HasVFPv2;
85  bool HasVFPv3;
86  bool HasVFPv4;
87  bool HasFPARMv8;
88  bool HasNEON;
89
90  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
91  /// specified. Use the method useNEONForSinglePrecisionFP() to
92  /// determine if NEON should actually be used.
93  bool UseNEONForSinglePrecisionFP;
94
95  /// UseMulOps - True if non-microcoded fused integer multiply-add and
96  /// multiply-subtract instructions should be used.
97  bool UseMulOps;
98
99  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
100  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
101  bool SlowFPVMLx;
102
103  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
104  /// forwarding to allow mul + mla being issued back to back.
105  bool HasVMLxForwarding;
106
107  /// SlowFPBrcc - True if floating point compare + branch is slow.
108  bool SlowFPBrcc;
109
110  /// InThumbMode - True if compiling for Thumb, false for ARM.
111  bool InThumbMode;
112
113  /// UseSoftFloat - True if we're using software floating point features.
114  bool UseSoftFloat;
115
116  /// HasThumb2 - True if Thumb2 instructions are supported.
117  bool HasThumb2;
118
119  /// NoARM - True if subtarget does not support ARM mode execution.
120  bool NoARM;
121
122  /// ReserveR9 - True if R9 is not available as a general purpose register.
123  bool ReserveR9;
124
125  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
126  /// 32-bit imms (including global addresses).
127  bool NoMovt;
128
129  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
130  /// must be able to synthesize call stubs for interworking between ARM and
131  /// Thumb.
132  bool SupportsTailCall;
133
134  /// HasFP16 - True if subtarget supports half-precision FP conversions
135  bool HasFP16;
136
137  /// HasFullFP16 - True if subtarget supports half-precision FP operations
138  bool HasFullFP16;
139
140  /// HasD16 - True if subtarget is limited to 16 double precision
141  /// FP registers for VFPv3.
142  bool HasD16;
143
144  /// HasHardwareDivide - True if subtarget supports [su]div
145  bool HasHardwareDivide;
146
147  /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
148  bool HasHardwareDivideInARM;
149
150  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
151  /// instructions.
152  bool HasT2ExtractPack;
153
154  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
155  /// instructions.
156  bool HasDataBarrier;
157
158  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
159  /// over 16-bit ones.
160  bool Pref32BitThumb;
161
162  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
163  /// that partially update CPSR and add false dependency on the previous
164  /// CPSR setting instruction.
165  bool AvoidCPSRPartialUpdate;
166
167  /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
168  /// movs with shifter operand (i.e. asr, lsl, lsr).
169  bool AvoidMOVsShifterOperand;
170
171  /// HasRAS - Some processors perform return stack prediction. CodeGen should
172  /// avoid issue "normal" call instructions to callees which do not return.
173  bool HasRAS;
174
175  /// HasMPExtension - True if the subtarget supports Multiprocessing
176  /// extension (ARMv7 only).
177  bool HasMPExtension;
178
179  /// HasVirtualization - True if the subtarget supports the Virtualization
180  /// extension.
181  bool HasVirtualization;
182
183  /// FPOnlySP - If true, the floating point unit only supports single
184  /// precision.
185  bool FPOnlySP;
186
187  /// If true, the processor supports the Performance Monitor Extensions. These
188  /// include a generic cycle-counter as well as more fine-grained (often
189  /// implementation-specific) events.
190  bool HasPerfMon;
191
192  /// HasTrustZone - if true, processor supports TrustZone security extensions
193  bool HasTrustZone;
194
195  /// HasCrypto - if true, processor supports Cryptography extensions
196  bool HasCrypto;
197
198  /// HasCRC - if true, processor supports CRC instructions
199  bool HasCRC;
200
201  /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
202  /// particularly effective at zeroing a VFP register.
203  bool HasZeroCycleZeroing;
204
205  /// StrictAlign - If true, the subtarget disallows unaligned memory
206  /// accesses for some types.  For details, see
207  /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
208  bool StrictAlign;
209
210  /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
211  ///  blocks to conform to ARMv8 rule.
212  bool RestrictIT;
213
214  /// HasDSP - If true, the subtarget supports the DSP (saturating arith
215  /// and such) instructions.
216  bool HasDSP;
217
218  /// NaCl TRAP instruction is generated instead of the regular TRAP.
219  bool UseNaClTrap;
220
221  /// Generate calls via indirect call instructions.
222  bool GenLongCalls;
223
224  /// Target machine allowed unsafe FP math (such as use of NEON fp)
225  bool UnsafeFPMath;
226
227  /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
228  bool UseSjLjEH;
229
230  /// stackAlignment - The minimum alignment known to hold of the stack frame on
231  /// entry to the function and which must be maintained by every function.
232  unsigned stackAlignment;
233
234  /// CPUString - String name of used CPU.
235  std::string CPUString;
236
237  /// IsLittle - The target is Little Endian
238  bool IsLittle;
239
240  /// TargetTriple - What processor and OS we're targeting.
241  Triple TargetTriple;
242
243  /// SchedModel - Processor specific instruction costs.
244  MCSchedModel SchedModel;
245
246  /// Selected instruction itineraries (one entry per itinerary class.)
247  InstrItineraryData InstrItins;
248
249  /// Options passed via command line that could influence the target
250  const TargetOptions &Options;
251
252  const ARMBaseTargetMachine &TM;
253
254public:
255  /// This constructor initializes the data members to match that
256  /// of the specified triple.
257  ///
258  ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
259               const ARMBaseTargetMachine &TM, bool IsLittle);
260
261  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
262  /// that still makes it profitable to inline the call.
263  unsigned getMaxInlineSizeThreshold() const {
264    return 64;
265  }
266  /// ParseSubtargetFeatures - Parses features string setting specified
267  /// subtarget options.  Definition of function is auto generated by tblgen.
268  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
269
270  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
271  /// so that we can use initializer lists for subtarget initialization.
272  ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
273
274  const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
275    return &TSInfo;
276  }
277  const ARMBaseInstrInfo *getInstrInfo() const override {
278    return InstrInfo.get();
279  }
280  const ARMTargetLowering *getTargetLowering() const override {
281    return &TLInfo;
282  }
283  const ARMFrameLowering *getFrameLowering() const override {
284    return FrameLowering.get();
285  }
286  const ARMBaseRegisterInfo *getRegisterInfo() const override {
287    return &InstrInfo->getRegisterInfo();
288  }
289
290private:
291  ARMSelectionDAGInfo TSInfo;
292  // Either Thumb1FrameLowering or ARMFrameLowering.
293  std::unique_ptr<ARMFrameLowering> FrameLowering;
294  // Either Thumb1InstrInfo or Thumb2InstrInfo.
295  std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
296  ARMTargetLowering   TLInfo;
297
298  void initializeEnvironment();
299  void initSubtargetFeatures(StringRef CPU, StringRef FS);
300  ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
301
302public:
303  void computeIssueWidth();
304
305  bool hasV4TOps()  const { return HasV4TOps;  }
306  bool hasV5TOps()  const { return HasV5TOps;  }
307  bool hasV5TEOps() const { return HasV5TEOps; }
308  bool hasV6Ops()   const { return HasV6Ops;   }
309  bool hasV6MOps()  const { return HasV6MOps;  }
310  bool hasV6KOps()  const { return HasV6KOps; }
311  bool hasV6T2Ops() const { return HasV6T2Ops; }
312  bool hasV7Ops()   const { return HasV7Ops;  }
313  bool hasV8Ops()   const { return HasV8Ops;  }
314  bool hasV8_1aOps() const { return HasV8_1aOps; }
315  bool hasV8_2aOps() const { return HasV8_2aOps; }
316
317  bool isCortexA5() const { return ARMProcFamily == CortexA5; }
318  bool isCortexA7() const { return ARMProcFamily == CortexA7; }
319  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
320  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
321  bool isCortexA15() const { return ARMProcFamily == CortexA15; }
322  bool isSwift()    const { return ARMProcFamily == Swift; }
323  bool isCortexM3() const { return CPUString == "cortex-m3"; }
324  bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
325  bool isCortexR5() const { return ARMProcFamily == CortexR5; }
326  bool isKrait() const { return ARMProcFamily == Krait; }
327
328  bool hasARMOps() const { return !NoARM; }
329
330  bool hasVFP2() const { return HasVFPv2; }
331  bool hasVFP3() const { return HasVFPv3; }
332  bool hasVFP4() const { return HasVFPv4; }
333  bool hasFPARMv8() const { return HasFPARMv8; }
334  bool hasNEON() const { return HasNEON;  }
335  bool hasCrypto() const { return HasCrypto; }
336  bool hasCRC() const { return HasCRC; }
337  bool hasVirtualization() const { return HasVirtualization; }
338  bool useNEONForSinglePrecisionFP() const {
339    return hasNEON() && UseNEONForSinglePrecisionFP;
340  }
341
342  bool hasDivide() const { return HasHardwareDivide; }
343  bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
344  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
345  bool hasDataBarrier() const { return HasDataBarrier; }
346  bool hasAnyDataBarrier() const {
347    return HasDataBarrier || (hasV6Ops() && !isThumb());
348  }
349  bool useMulOps() const { return UseMulOps; }
350  bool useFPVMLx() const { return !SlowFPVMLx; }
351  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
352  bool isFPBrccSlow() const { return SlowFPBrcc; }
353  bool isFPOnlySP() const { return FPOnlySP; }
354  bool hasPerfMon() const { return HasPerfMon; }
355  bool hasTrustZone() const { return HasTrustZone; }
356  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
357  bool prefers32BitThumb() const { return Pref32BitThumb; }
358  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
359  bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
360  bool hasRAS() const { return HasRAS; }
361  bool hasMPExtension() const { return HasMPExtension; }
362  bool hasDSP() const { return HasDSP; }
363  bool useNaClTrap() const { return UseNaClTrap; }
364  bool useSjLjEH() const { return UseSjLjEH; }
365  bool genLongCalls() const { return GenLongCalls; }
366
367  bool hasFP16() const { return HasFP16; }
368  bool hasD16() const { return HasD16; }
369  bool hasFullFP16() const { return HasFullFP16; }
370
371  const Triple &getTargetTriple() const { return TargetTriple; }
372
373  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
374  bool isTargetIOS() const { return TargetTriple.isiOS(); }
375  bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
376  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
377  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
378  bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
379  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
380
381  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
382  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
383  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
384
385  // ARM EABI is the bare-metal EABI described in ARM ABI documents and
386  // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
387  // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
388  // even for GNUEABI, so we can make a distinction here and still conform to
389  // the EABI on GNU (and Android) mode. This requires change in Clang, too.
390  // FIXME: The Darwin exception is temporary, while we move users to
391  // "*-*-*-macho" triples as quickly as possible.
392  bool isTargetAEABI() const {
393    return (TargetTriple.getEnvironment() == Triple::EABI ||
394            TargetTriple.getEnvironment() == Triple::EABIHF) &&
395           !isTargetDarwin() && !isTargetWindows();
396  }
397  bool isTargetGNUAEABI() const {
398    return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
399            TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
400           !isTargetDarwin() && !isTargetWindows();
401  }
402
403  // ARM Targets that support EHABI exception handling standard
404  // Darwin uses SjLj. Other targets might need more checks.
405  bool isTargetEHABICompatible() const {
406    return (TargetTriple.getEnvironment() == Triple::EABI ||
407            TargetTriple.getEnvironment() == Triple::GNUEABI ||
408            TargetTriple.getEnvironment() == Triple::EABIHF ||
409            TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
410            isTargetAndroid()) &&
411           !isTargetDarwin() && !isTargetWindows();
412  }
413
414  bool isTargetHardFloat() const {
415    // FIXME: this is invalid for WindowsCE
416    return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
417           TargetTriple.getEnvironment() == Triple::EABIHF ||
418           isTargetWindows() || isAAPCS16_ABI();
419  }
420  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
421
422  bool isAPCS_ABI() const;
423  bool isAAPCS_ABI() const;
424  bool isAAPCS16_ABI() const;
425
426  bool useSoftFloat() const { return UseSoftFloat; }
427  bool isThumb() const { return InThumbMode; }
428  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
429  bool isThumb2() const { return InThumbMode && HasThumb2; }
430  bool hasThumb2() const { return HasThumb2; }
431  bool isMClass() const { return ARMProcClass == MClass; }
432  bool isRClass() const { return ARMProcClass == RClass; }
433  bool isAClass() const { return ARMProcClass == AClass; }
434
435  bool isR9Reserved() const {
436    return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
437  }
438
439  bool useStride4VFPs(const MachineFunction &MF) const;
440
441  bool useMovt(const MachineFunction &MF) const;
442
443  bool supportsTailCall() const { return SupportsTailCall; }
444
445  bool allowsUnalignedMem() const { return !StrictAlign; }
446
447  bool restrictIT() const { return RestrictIT; }
448
449  const std::string & getCPUString() const { return CPUString; }
450
451  bool isLittle() const { return IsLittle; }
452
453  unsigned getMispredictionPenalty() const;
454
455  /// This function returns true if the target has sincos() routine in its
456  /// compiler runtime or math libraries.
457  bool hasSinCos() const;
458
459  /// Returns true if machine scheduler should be enabled.
460  bool enableMachineScheduler() const override;
461
462  /// True for some subtargets at > -O0.
463  bool enablePostRAScheduler() const override;
464
465  // enableAtomicExpand- True if we need to expand our atomics.
466  bool enableAtomicExpand() const override;
467
468  /// getInstrItins - Return the instruction itineraries based on subtarget
469  /// selection.
470  const InstrItineraryData *getInstrItineraryData() const override {
471    return &InstrItins;
472  }
473
474  /// getStackAlignment - Returns the minimum alignment known to hold of the
475  /// stack frame on entry to the function and which must be maintained by every
476  /// function for this subtarget.
477  unsigned getStackAlignment() const { return stackAlignment; }
478
479  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
480  /// symbol.
481  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
482
483  /// True if fast-isel is used.
484  bool useFastISel() const;
485};
486} // End llvm namespace
487
488#endif  // ARMSUBTARGET_H
489