Searched refs:ShiftAmount (Results 1 - 11 of 11) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp197 unsigned ShiftAmount; member in struct:__anon2707::AArch64Operand::ShiftedImmOp
349 return ShiftedImm.ShiftAmount;
702 unsigned Shift = ShiftedImm.ShiftAmount;
740 unsigned Shift = ShiftedImm.ShiftAmount;
1285 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0;
1681 unsigned ShiftAmount,
1686 Op->ShiftedImm.ShiftAmount = ShiftAmount;
2297 uint64_t ShiftAmount = 0; local
2303 ShiftAmount
1680 CreateShiftedImm(const MCExpr *Val, unsigned ShiftAmount, SMLoc S, SMLoc E, MCContext &Ctx) argument
2334 int64_t ShiftAmount = Parser.getTok().getIntVal(); local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp849 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); local
851 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
852 ShiftAmount);
H A DLegalizeDAG.cpp412 SDValue ShiftAmount = local
416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
580 SDValue ShiftAmount = local
583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
1746 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1748 if (ShiftAmount > 0) {
1749 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
1751 } else if (ShiftAmount < 0) {
1752 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
1758 if (ShiftAmount >
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp758 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); local
765 if (Opc == ISD::SRL && ShiftAmount) {
769 ShiftAmount -= 1;
772 while (ShiftAmount--)
/freebsd-11.0-release/contrib/llvm/lib/Analysis/
H A DInstructionSimplify.cpp2326 unsigned ShiftAmount = CI2->getValue().countLeadingOnes() - 1; local
2327 Lower = CI2->getValue().shl(ShiftAmount);
2331 unsigned ShiftAmount = CI2->getValue().countLeadingZeros() - 1; local
2333 Upper = CI2->getValue().shl(ShiftAmount) + 1;
2342 unsigned ShiftAmount = Width - 1; local
2344 ShiftAmount = CI2->getValue().countTrailingZeros();
2345 Lower = CI2->getValue().lshr(ShiftAmount);
2356 unsigned ShiftAmount = Width - 1; local
2358 ShiftAmount = CI2->getValue().countTrailingZeros();
2362 Upper = CI2->getValue().ashr(ShiftAmount)
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp457 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; local
459 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0))
470 unsigned Elt = ShiftAmount / DestWidth;
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1500 void emitAppropriateDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount, argument
1502 if (ShiftAmount >= 32) {
1503 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc,
1508 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, Instructions);
2268 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); local
2269 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2271 emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, Instructions);
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp205 unsigned &ShiftAmount);
4137 const MCExpr *ShiftAmount; local
4140 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4144 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4220 const MCExpr *ShiftAmount; local
4222 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4226 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4282 const MCExpr *ShiftAmount; local
4284 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4288 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1916 SDValue &Src, int &ShiftAmount,
1951 ShiftAmount = countTrailingZeros(NonZeroBits);
1952 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount);
1959 if (ShlImm - ShiftAmount != 0 && !BiggerPattern)
1961 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount);
1914 isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, SDValue &Src, int &ShiftAmount, int &MaskWidth) argument
H A DAArch64ISelLowering.cpp7692 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, argument
7704 ShiftAmount = N->getConstantOperandVal(1);
8296 int64_t ShiftAmount; local
8306 ShiftAmount = SplatValue.getSExtValue();
8308 ShiftAmount = CVN->getSExtValue();
8339 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) {
8342 DAG.getConstant(-ShiftAmount, dl, MVT::i32));
8343 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBit
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1319 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32); local
1320 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1341 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);

Completed in 356 milliseconds