/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 26 case ISD::SHL: return ARM_AM::lsl;
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/freebsd-11.0-release/usr.bin/xlint/lint1/ |
H A D | op.h | 79 SHL, enumerator in enum:__anon13870
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H A D | tree.c | 131 { SHL, { 1,0,1,0,0,1,1,0,0,0,0,0,1,0,0,1,1, 614 if (mp->m_balance || (tflag && (op == SHL || op == SHR))) 646 case SHL: 812 if (op == SHL || op == SHR || op == SHLASS || op == SHRASS) { 967 case SHL: 973 * width of the right operand. For SHL this may result in 2490 * Create a node for operators SHL and SHR. 2809 case SHL: 3608 case SHL: 3944 case SHL [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 135 { ISD::SHL, MVT::v16i32, 1 }, 138 { ISD::SHL, MVT::v8i64, 1 }, 151 { ISD::SHL, MVT::v4i32, 1 }, 154 { ISD::SHL, MVT::v8i32, 1 }, 157 { ISD::SHL, MVT::v2i64, 1 }, 159 { ISD::SHL, MVT::v4i64, 1 }, 165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && 178 { ISD::SHL, MVT::v16i8, 1 }, 181 { ISD::SHL, MVT::v8i16, 1 }, 184 { ISD::SHL, MV [all...] |
H A D | X86IntrinsicsInfo.h | 310 X86_INTRINSIC_DATA(avx2_psllv_d, INTR_TYPE_2OP, ISD::SHL, 0), 311 X86_INTRINSIC_DATA(avx2_psllv_d_256, INTR_TYPE_2OP, ISD::SHL, 0), 312 X86_INTRINSIC_DATA(avx2_psllv_q, INTR_TYPE_2OP, ISD::SHL, 0), 313 X86_INTRINSIC_DATA(avx2_psllv_q_256, INTR_TYPE_2OP, ISD::SHL, 0), 1356 X86_INTRINSIC_DATA(avx512_mask_psllv16_hi, INTR_TYPE_2OP_MASK, ISD::SHL, 0), 1357 X86_INTRINSIC_DATA(avx512_mask_psllv2_di, INTR_TYPE_2OP_MASK, ISD::SHL, 0), 1358 X86_INTRINSIC_DATA(avx512_mask_psllv32hi, INTR_TYPE_2OP_MASK, ISD::SHL, 0), 1359 X86_INTRINSIC_DATA(avx512_mask_psllv4_di, INTR_TYPE_2OP_MASK, ISD::SHL, 0), 1360 X86_INTRINSIC_DATA(avx512_mask_psllv4_si, INTR_TYPE_2OP_MASK, ISD::SHL, 0), 1361 X86_INTRINSIC_DATA(avx512_mask_psllv8_hi, INTR_TYPE_2OP_MASK, ISD::SHL, [all...] |
H A D | X86ISelDAGToDAG.cpp | 932 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount); 958 if (Shift.getOpcode() != ISD::SHL || 977 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); 1084 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt); 1168 case ISD::SHL: 1361 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; 2321 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL
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H A D | MSP430ISelLowering.cpp | 92 setOperationAction(ISD::SHL, MVT::i8, Custom); 95 setOperationAction(ISD::SHL, MVT::i16, Custom); 186 case ISD::SHL: // FALLTHROUGH 747 case ISD::SHL: 748 return DAG.getNode(MSP430ISD::SHL, dl, 773 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), 1152 case MSP430ISD::SHL: return "MSP430ISD::SHL";
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 83 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 633 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS); 841 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 916 case ISD::SHL: 1039 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 1386 case ISD::SHL: 1423 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>. 1435 if (N->getOpcode() == ISD::SHL) { 1440 Hi = DAG.getNode(ISD::SHL, DL, 1455 Lo = DAG.getNode(ISD::SHL, D [all...] |
H A D | LegalizeVectorOps.cpp | 279 case ISD::SHL: 590 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt); 610 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); 792 // Make sure that the SRA and SHL instructions are available. 794 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) 805 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); 851 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), 920 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) || 994 // Notice that we can also use SHL+SHR, but using a constant is slightly
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H A D | TargetLowering.cpp | 612 case ISD::SHL: 628 unsigned Opc = ISD::SHL; 654 isTypeDesirableForOp(ISD::SHL, InnerVT)) { 659 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, 666 // Repeat the SHL optimization above in cases where an extension 687 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, 720 if (InOp.getOpcode() == ISD::SHL && 728 Opc = ISD::SHL; 838 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, 1071 // Cannot eliminate/lower SHL fo [all...] |
H A D | LegalizeDAG.cpp | 583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 1048 ISD::SHL, dl, Hi.getValueType(), Hi, 1080 ISD::SHL, dl, Hi.getValueType(), Hi, 1357 case ISD::SHL: 1753 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); 1763 SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst); 2848 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT)); 2870 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); 2874 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT)); 2875 Tmp3 = DAG.getNode(ISD::SHL, d [all...] |
H A D | DAGCombiner.cpp | 1385 case ISD::SHL: return visitSHL(N); 1484 case ISD::SHL: 1742 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB && 1745 DAG.getNode(ISD::SHL, SDLoc(N), VT, 1748 if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB && 1751 DAG.getNode(ISD::SHL, SDLoc(N), VT, 2073 return DAG.getNode(ISD::SHL, DL, VT, N0, 2086 DAG.getNode(ISD::SHL, DL, VT, N0, 2093 if (N1IsConst && N0.getOpcode() == ISD::SHL && 2096 SDValue C3 = DAG.getNode(ISD::SHL, SDLo [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType 405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 1318 // SHL 16, then OR base and base+2. 1320 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount); 1340 // SHL 16, then OR base+4 and base+6. 1341 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount); 1783 setOperationAction(ISD::SHL, VT, Custom); 2149 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific 2150 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>. 2176 case ISD::SHL: 2190 case ISD::SHL: 2311 SDValue Shifted = DAG.getNode(ISD::SHL, d [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 763 if (Shl.getOpcode() != ISD::SHL) 1930 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1933 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1980 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1990 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 2095 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); 2097 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); 2130 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, 2132 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); 2225 SDValue SLL = DAG.getNode(ISD::SHL, D [all...] |
H A D | MipsSEISelLowering.cpp | 76 setTargetDAGCombine(ISD::SHL); 268 setOperationAction(ISD::SHL, Ty, Legal); 811 return DAG.getNode(ISD::SHL, DL, VT, X, 890 // the ISD::SRA and ISD::SHL nodes. 891 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 909 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 1085 case ISD::SHL: 1491 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy), 1502 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); 1633 DAG.getNode(ISD::SHL, D [all...] |
/freebsd-11.0-release/crypto/openssl/crypto/sha/asm/ |
H A D | sha512-ppc.pl | 45 $SHL="sldi"; 53 $SHL="slwi"; 193 $SHL $num,$num,`log(16*$SZ)/log(2)`
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 488 if (Opcode == ISD::SHL) { 539 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 541 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 548 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 549 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 561 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 564 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 575 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask && 580 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 936 case ISD::SHL [all...] |
H A D | PPCISelLowering.h | 94 SRL, SRA, SHL,
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 310 setOperationAction(ISD::SHL, VT, Expand); 379 setTargetDAGCombine(ISD::SHL); 1308 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift); 1469 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, 1533 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, 1541 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, 1544 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, 1717 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); 2282 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ), 2292 DAG.getNode(ISD::SHL, S [all...] |
H A D | R600ISelLowering.cpp | 1010 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); 1012 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); 1014 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); 1045 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); 1046 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); 1343 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, 1345 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, Shift); 1346 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, Shift);
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/freebsd-11.0-release/crypto/openssl/crypto/bn/asm/ |
H A D | ppc.pl | 120 $SHL= "slw"; # shift left 144 $SHL= "sld"; # shift left 1654 $SHL r3,r3,r7 # h = (h<< i) 1656 $SHL r5,r5,r7 # d<<=i 1658 $SHL r4,r4,r7 # l <<=i
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 316 case ISD::SHL: 566 if (N.getOpcode() == ISD::SHL) { 769 /// \brief Check if the given SHL node (\p N), can be used to form an 774 assert(N.getOpcode() == ISD::SHL && "Invalid opcode."); 834 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL && 842 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL && 947 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL && 955 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL && 1578 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) { 1881 /// Create a machine node performing a notional SHL o [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 160 // For others we will expand to a SHL/SRA pair. 281 setTargetDAGCombine(ISD::SHL); 1732 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 1773 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 1791 SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 1796 SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 1801 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4159 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift 4180 // If we have a SHL, determine the actual multiply amount 4181 if (N->getOpcode() == ISD::SHL) { [all...] |