Lines Matching refs:SHL
76 setTargetDAGCombine(ISD::SHL);
268 setOperationAction(ISD::SHL, Ty, Legal);
811 return DAG.getNode(ISD::SHL, DL, VT, X,
890 // the ISD::SRA and ISD::SHL nodes.
891 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
909 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
1085 case ISD::SHL:
1491 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1502 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1633 DAG.getNode(ISD::SHL, DL, VecTy, One,
1669 DAG.getNode(ISD::SHL, DL, VecTy, One,
1960 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
2095 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2101 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),