/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 330 /// in the set, or Regs.size() if they are all allocated. 331 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { 332 for (unsigned i = 0; i < Regs.size(); ++i) 333 if (!isAllocated(Regs[i])) 335 return Regs.size(); 358 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { argument 359 unsigned FirstUnalloc = getFirstUnallocated(Regs); 360 if (FirstUnalloc == Regs.size()) 364 unsigned Reg = Regs[FirstUnalloc]; 372 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigne argument 399 AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) argument [all...] |
H A D | RegisterPressure.h | 228 SparseSet<unsigned> Regs; 249 return Regs.count(SparseIndex); 254 return Regs.insert(SparseIndex).second; 259 return Regs.erase(SparseIndex); 263 return Regs.size(); 268 for (unsigned I : Regs) { 346 void addLiveRegs(ArrayRef<unsigned> Regs); 479 void increaseRegPressure(ArrayRef<unsigned> Regs); 480 void decreaseRegPressure(ArrayRef<unsigned> Regs);
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 50 const unsigned *Regs, unsigned Size) { 52 RegNo = Regs[RegNo]; 228 const unsigned *Regs) { 232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 238 const unsigned *Regs) { 242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 248 const unsigned *Regs) { 253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 255 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); 260 const unsigned *Regs) { 49 decodeRegisterClass(MCInst &Inst, uint64_t RegNo, const unsigned *Regs, unsigned Size) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMUnwindOpAsm.cpp | 106 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { 107 while (Regs) { 109 auto RangeMSB = 32 - countLeadingZeros(Regs); 110 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); 120 Regs &= ~(-1u << RangeLSB);
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/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs, 59 const std::deque<CodeGenRegister> &Regs, 183 const CodeGenRegister::Vec &Regs = RC.getMembers(); local 184 if (Regs.empty()) 189 OS << " {" << (*Regs.begin())->getWeight(RegBank) 321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 328 for (auto &RE : Regs) { 347 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 395 for (auto &RE : Regs) { 444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, boo 320 EmitRegMappingTables( raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) argument 443 EmitRegMapping( raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) argument 790 const auto &Regs = RegBank.getRegisters(); local 1325 const auto &Regs = RegBank.getRegisters(); local 1423 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); local [all...] |
H A D | CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs): argument 161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 940 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); local 941 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); 943 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 944 getReg(Regs[i]); 1298 CodeGenRegister::Vec Regs; member in struct:__anon4582::UberRegSet 1327 const CodeGenRegister::Vec &Regs local 2087 computeCoveredRegisters(ArrayRef<Record*> Regs) argument [all...] |
H A D | CodeGenTarget.cpp | 235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); local 236 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); 237 if (I == Regs.end())
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegisterInfo.cpp | 96 static const unsigned Regs[2][2] = { local 101 return Regs[TFI->hasFP(MF)][TT.isArch64Bit()];
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 367 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 371 RegisterGroup Group, const unsigned *Regs, 376 const unsigned *Regs, RegisterKind RegKind); 379 MemoryKind MemKind, const unsigned *Regs, 534 // Parse a register of group Group. If Regs is nonnull, use it to map 541 const unsigned *Regs, bool IsAddress) { 546 if (Regs && Regs[Reg.Num] == 0) 550 if (Regs) 551 Reg.Num = Regs[Re 540 parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress) argument 557 parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) argument 575 parseAddress(unsigned &Base, const MCExpr *&Disp, unsigned &Index, bool &IsVector, const MCExpr *&Length, const unsigned *Regs, RegisterKind RegKind) argument 637 parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | ExecutionDepsFix.cpp | 648 SmallVector<LiveReg, 4> Regs; local 660 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); 664 Regs.insert(i, LR); 668 Regs.push_back(LR); 674 while (!Regs.empty()) { 676 dv = Regs.pop_back_val().Value; 683 DomainValue *Latest = Regs.pop_back_val().Value;
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H A D | AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs, 75 Regs.push_back(Reg); 544 std::vector<unsigned> Regs; 545 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); 546 assert(Regs.size() > 0 && "Empty register group!"); 547 if (Regs.size() == 0) 557 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 558 unsigned Reg = Regs[i]; 577 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 578 unsigned Reg = Regs[ 68 GetGroupRegs( unsigned Group, std::vector<unsigned> &Regs, std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs) argument [all...] |
H A D | AggressiveAntiDepBreaker.h | 94 std::vector<unsigned> &Regs,
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H A D | CallingConvLower.cpp | 193 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, argument 222 Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
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H A D | RegisterPressure.cpp | 165 Regs.setUniverse(NumRegUnits + NumVirtRegs); 170 Regs.clear(); 468 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { argument 469 for (unsigned Reg : Regs) {
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 140 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs); 144 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const; 534 /// Return the first register of class \p RegClass that is not in \p Regs. 566 static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs, argument 568 for (const std::pair<unsigned, bool> &R : Regs) 575 /// Regs as the register operands that would be loaded / stored. It returns 580 DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) { 581 unsigned NumRegs = Regs.size(); 595 if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) { 636 NewBase = Regs[NumReg 577 CreateLoadStoreMulti(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base, bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) argument 800 SmallVector<std::pair<unsigned, bool>, 8> Regs; local [all...] |
H A D | ARMFrameLowering.cpp | 901 SmallVector<std::pair<unsigned,bool>, 4> Regs; local 933 Regs.push_back(std::make_pair(Reg, isKill)); 936 if (Regs.empty()) 938 if (Regs.size() > 1 || StrOpc== 0) { 942 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 943 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 944 } else if (Regs.size() == 1) { 947 .addReg(Regs[0].first, getKillRegState(Regs[ 987 SmallVector<unsigned, 4> Regs; local [all...] |
H A D | Thumb2SizeReduction.cpp | 221 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) 222 if (*Regs == ARM::CPSR)
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 171 BitVector &Regs) { 179 applyToClobberedRegisters(MI, TRI, [&](unsigned r) { Regs.set(r); }); 169 collectChangingRegs(const MachineFunction *MF, const TargetRegisterInfo *TRI, BitVector &Regs) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 971 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { argument 977 return createTuple(Regs, RegClassIDs, SubRegs); 980 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { argument 986 return createTuple(Regs, RegClassIDs, SubRegs); 989 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, argument 994 if (Regs.size() == 1) 995 return Regs[0]; 997 assert(Regs.size() >= 2 && Regs.size() <= 4); 999 SDLoc DL(Regs[ [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenInsert.cpp | 961 RegisterSet Regs[2]; 964 Regs[S].insert(VR); 966 while (!Regs[S].empty()) { 969 Regs[OtherS].clear(); 970 for (unsigned R = Regs[S].find_first(); R; R = Regs[S].find_next(R)) { 971 Regs[S].remove(R); 994 getInstrUses(DefI, Regs[OtherS]); 1448 SmallVector<unsigned,2> Regs; 1458 Regs [all...] |
H A D | HexagonFrameLowering.cpp | 1184 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) { argument 1186 for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) { 1436 BitVector Regs(Hexagon::NUM_TARGET_REGS); 1441 Regs[R] = true; 1443 int F = Regs.find_first(); 1447 int N = Regs.find_next(F);
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineScheduler.h | 388 void addLiveRegs(std::set<unsigned> &Regs); 389 void decreaseLiveRegs(SIScheduleBlock *Block, std::set<unsigned> &Regs);
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/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 668 SDValue Regs[2]; local 669 if (selectBDXAddr12Only(Addr, Regs[0], Disp, Regs[1]) && 670 Regs[0].getNode() && Regs[1].getNode()) { 672 Base = Regs[I]; 673 Index = Regs[1 - I];
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/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 899 SmallPtrSetImpl<const SCEV *> &Regs, 912 SmallPtrSetImpl<const SCEV *> &Regs, 916 SmallPtrSetImpl<const SCEV *> &Regs, 926 SmallPtrSetImpl<const SCEV *> &Regs, 948 if (!Regs.count(AR->getOperand(1))) { 949 RateRegister(AR->getOperand(1), Regs, L, SE, DT); 974 SmallPtrSetImpl<const SCEV *> &Regs, 982 if (Regs.insert(Reg).second) { 983 RateRegister(Reg, Regs, L, SE, DT); 991 SmallPtrSetImpl<const SCEV *> &Regs, 925 RateRegister(const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT) argument 973 RatePrimaryRegister(const SCEV *Reg, SmallPtrSetImpl<const SCEV *> &Regs, const Loop *L, ScalarEvolution &SE, DominatorTree &DT, SmallPtrSetImpl<const SCEV *> *LoserRegs) argument 989 RateFormula(const TargetTransformInfo &TTI, const Formula &F, SmallPtrSetImpl<const SCEV *> &Regs, const DenseSet<const SCEV *> &VisitedRegs, const Loop *L, const SmallVectorImpl<int64_t> &Offsets, ScalarEvolution &SE, DominatorTree &DT, const LSRUse &LU, SmallPtrSetImpl<const SCEV *> *LoserRegs) argument 1248 SmallPtrSet<const SCEV *, 4> Regs; member in class:__anon3215::LSRUse 3864 SmallPtrSet<const SCEV *, 16> Regs; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.h | 915 /// Regs - This list holds the registers assigned to the values. 919 SmallVector<unsigned, 4> Regs; member in struct:llvm::RegsForValue 932 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
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