Searched refs:RegNum (Results 1 - 21 of 21) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
65 DwarfLLVMRegPair Key = { RegNum, 0 };
67 if (I == M+Size || I->FromReg != RegNum)
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
76 DwarfLLVMRegPair Key = { RegNum, 0 };
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const {
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
84 if (I == L2SEHRegs.end()) return (int)RegNum;
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp184 unsigned RegNum; member in struct:__anon2822::HexagonOperand::RegTy
230 return Reg.RegNum;
582 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, argument
585 Op->Reg.RegNum = RegNum;
1989 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
1990 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1993 r + llvm::utostr_32(RegNum) + Colon + llvm::utostr_32(RegNum - 1);
1999 r + llvm::utostr_32(RegNum
2008 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); local
2027 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
2049 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
2074 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DStackMaps.cpp79 int RegNum = TRI->getDwarfRegNum(Reg, false); local
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
81 RegNum = TRI->getDwarfRegNum(*SR, false);
83 assert(RegNum >= 0 && "Invalid Dwarf register number.");
84 return (unsigned)RegNum;
450 /// uint16 : Dwarf RegNum
456 /// uint16 : Dwarf RegNum
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp176 unsigned RegNum; member in struct:__anon2707::AArch64Operand::RegOp
181 unsigned RegNum; member in struct:__anon2707::AArch64Operand::VectorListOp
374 return Reg.RegNum;
379 return VectorList.RegNum;
925 Reg.RegNum);
929 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
934 Reg.RegNum);
939 Reg.RegNum);
944 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
1640 CreateReg(unsigned RegNum, boo argument
1650 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, char ElementKind, SMLoc S, SMLoc E, MCContext &Ctx) argument
1958 unsigned RegNum = isVector ? matchVectorRegName(Name) local
1984 unsigned RegNum = matchRegisterNameAlias(lowerCase, false); local
2015 unsigned RegNum = matchRegisterNameAlias(Head, true); local
3113 unsigned RegNum = matchRegisterNameAlias(Tok.getString().lower(), false); local
4370 unsigned RegNum = tryParseRegister(); local
[all...]
/freebsd-11.0-release/contrib/llvm/include/llvm/MC/
H A DMCRegisterInfo.h390 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
393 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
397 int getSEHRegNum(unsigned RegNum) const;
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp184 unsigned RegNum; member in struct:__anon2995::SparcOperand::RegOp
235 return Reg.RegNum;
329 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, argument
332 Op->Reg.RegNum = RegNum;
362 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
373 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
396 Op.Reg.RegNum = Reg;
/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Basic/
H A DTargetInfo.cpp377 if (AN == Name && ARN.RegNum < Names.size())
418 if (AN == Name && ARN.RegNum < Names.size())
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp469 unsigned RegNum; member in struct:__anon2788::ARMOperand::RegOp
474 unsigned RegNum; member in struct:__anon2788::ARMOperand::VectorListOp
503 unsigned RegNum; member in struct:__anon2788::ARMOperand::PostIdxRegOp
600 return Reg.RegNum;
1367 .contains(VectorList.RegNum));
1384 .contains(VectorList.RegNum));
1411 .contains(VectorList.RegNum));
1686 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; local
1687 Inst.addOperand(MCOperand::createReg(RegNum));
2109 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2515 CreateCCOut(unsigned RegNum, SMLoc S) argument
2532 CreateReg(unsigned RegNum, SMLoc S, SMLoc E) argument
2630 CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2644 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2656 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) argument
2706 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
2920 unsigned RegNum = MatchRegisterName(lowerCase); local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp265 unsigned RegNum = TRI->getEncodingValue(Reg); local
270 FPUBitmask |= (1 << RegNum);
273 FPUBitmask |= (3 << RegNum);
277 CPUBitmask |= (1 << RegNum);
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
518 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
524 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
529 int NewOpcode, int RegNum) {
534 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
517 insertCondBranchBefore(MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, DebugLoc DL) argument
528 insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum) argument
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp2011 unsigned RegNum;
2019 RegNum = RegLst & 0xf;
2022 if (RegNum > 9)
2025 for (unsigned i = 0; i < RegNum; i++)
2048 unsigned RegNum = RegLst & 0x3;
2050 for (unsigned i = 0; i <= RegNum; i++)
/freebsd-11.0-release/contrib/llvm/tools/clang/include/clang/Basic/
H A DTargetInfo.h727 const unsigned RegNum; member in struct:clang::TargetInfo::AddlRegName
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1472 unsigned RegNum = GetX86RegNum(MO) << 4; local
1474 RegNum |= 1 << 7;
1482 RegNum |= Val;
1485 EmitImmediate(MCOperand::createImm(RegNum), MI.getLoc(), 1, FK_Data_1,
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp968 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); local
972 if (RegNum <= PRegNum)
977 else if (!isNotVFP && RegNum != PRegNum+1)
996 PRegNum = RegNum;
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1342 unsigned RegNum = Reg.EnumValue; local
1343 if (AllocatableRegs.count(RegNum))
1346 UberSetIDs.join(0, RegNum);
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1030 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1031 return X86ATTInstPrinter::getRegisterName(RegNum);
H A DX86ISelLowering.cpp[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp1123 if (unsigned RegNum = MO2.getReg()) {
1125 printRegName(O, RegNum);
/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp304 unsigned RegNum = RegMap[Reg]; local
326 Ret |= (RegNum & 0x0FFFFFFF);
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp306 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
3879 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { argument
3880 if (RegNum >
3884 return getReg(RegClass, RegNum);
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2584 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
2588 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2589 // need to skip a register if RegNum is odd.
2590 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2591 State.AllocateReg(ArgRegs[RegNum]);
2612 unsigned RegNum = State.getFirstUnallocated(ArgRegs); local
2616 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2617 State.AllocateReg(ArgRegs[RegNum]);
[all...]

Completed in 574 milliseconds