Searched refs:Inst (Results 1 - 25 of 258) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/lib/MC/
H A DMCInstrAnalysis.cpp13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, argument
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
/freebsd-11.0-release/contrib/llvm/include/llvm/MC/
H A DMCInstrAnalysis.h34 virtual bool isBranch(const MCInst &Inst) const {
35 return Info->get(Inst.getOpcode()).isBranch();
38 virtual bool isConditionalBranch(const MCInst &Inst) const {
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
42 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
46 virtual bool isIndirectBranch(const MCInst &Inst) const {
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
50 virtual bool isCall(const MCInst &Inst) const {
51 return Info->get(Inst
[all...]
H A DMCInstBuilder.h23 MCInst Inst; member in class:llvm::MCInstBuilder
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::createReg(Reg));
39 Inst.addOperand(MCOperand::createImm(Val));
45 Inst.addOperand(MCOperand::createFPImm(Val));
51 Inst.addOperand(MCOperand::createExpr(Val));
57 Inst.addOperand(MCOperand::createInst(Val));
63 Inst.addOperand(Op);
68 return Inst;
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp49 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, argument
55 Inst.addOperand(MCOperand::createReg(RegNo));
59 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
62 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
65 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
68 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
71 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
74 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
77 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
80 return decodeRegisterClass(Inst, RegN
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
199 DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
211 DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
223 DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
234 DecodeNegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
275 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
345 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
358 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
371 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
384 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
398 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
411 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
424 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
438 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
509 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
523 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
537 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
550 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
563 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
576 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
589 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
603 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
618 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
632 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
646 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
666 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
680 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
700 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
719 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64AddressTypePromotion.cpp109 /// - Inst is used only once (no need to insert truncate).
110 /// - Inst has only one operand that will require a sext operation (we do
112 bool shouldGetThrough(const Instruction *Inst);
120 bool canGetThrough(const Instruction *Inst);
157 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) { argument
158 if (isa<SExtInst>(Inst))
161 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
167 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
168 const Instruction *Opnd = cast<Instruction>(Inst
180 shouldGetThrough(const Instruction *Inst) argument
209 shouldSExtOperand(const Instruction *Inst, int OpIdx) argument
393 << *Inst << '\\n'); local
442 const Instruction *Inst = dyn_cast<GetElementPtrInst>(U); local
453 Instruction *Inst = SExt; local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Transforms/Scalar/
H A DSink.cpp60 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
61 bool IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const;
76 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst, argument
82 for (Use &U : Inst->uses()) {
137 Instruction *Inst = &*I; // The instruction to sink. local
145 if (isa<DbgInfoIntrinsic>(Inst))
148 if (SinkInstruction(Inst, Stores))
157 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA, argument
160 if (Inst->mayWriteToMemory()) {
161 Stores.insert(Inst);
188 IsAcceptableTarget(Instruction *Inst, BasicBlock *SuccToSinkTo) const argument
232 SinkInstruction(Instruction *Inst, SmallPtrSetImpl<Instruction *> &Stores) argument
[all...]
H A DEarlyCSE.cpp54 Instruction *Inst; member in struct:__anon3179::SimpleValue
56 SimpleValue(Instruction *I) : Inst(I) {
57 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
61 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() ||
62 Inst == DenseMapInfo<Instruction *>::getTombstoneKey();
65 static bool canHandle(Instruction *Inst) { argument
67 if (CallInst *CI = dyn_cast<CallInst>(Inst))
69 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
70 isa<GetElementPtrInst>(Inst) || is
92 Instruction *Inst = Val.Inst; local
201 Instruction *Inst; member in struct:__anon3180::CallValue
212 canHandle(Instruction *Inst) argument
239 Instruction *Inst = Val.Inst; local
400 ParseMemoryInst(Instruction *Inst, const TargetTransformInfo &TTI) argument
485 Instruction *Inst; member in class:__anon3181::EarlyCSE::ParseMemoryInst
490 getOrCreateResult(Value *Inst, Type *ExpectedType) const argument
550 Instruction *Inst = &*I++; local
729 << " due to: " << *Inst << '\\n'); local
[all...]
H A DConstantHoisting.cpp66 Instruction *Inst; member in struct:__anon3172::ConstantUser
69 ConstantUser(Instruction *Inst, unsigned Idx) : Inst(Inst), OpndIdx(Idx) { } argument
82 void addUser(Instruction *Inst, unsigned Idx, unsigned Cost) { argument
84 Uses.push_back(ConstantUser(Inst, Idx));
157 Instruction *findMatInsertPt(Instruction *Inst, unsigned Idx = ~0U) const;
160 Instruction *Inst, unsigned Idx,
163 Instruction *Inst);
214 Instruction *ConstantHoisting::findMatInsertPt(Instruction *Inst, argument
275 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst, unsigned Idx, ConstantInt *ConstInt) argument
312 collectConstantCandidates(ConstCandMapType &ConstCandMap, Instruction *Inst) argument
445 updateOperand(Instruction *Inst, unsigned Idx, Instruction *Mat) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Analysis/
H A DOrderedBasicBlock.cpp37 const Instruction *Inst = nullptr; local
49 Inst = cast<Instruction>(II);
50 NumberedInsts[Inst] = NextInstPos++;
51 if (Inst == A || Inst == B)
56 assert((Inst == A || Inst == B) && "Should find A or B");
58 return Inst == A;
H A DCFLAliasAnalysis.cpp72 // Returns possible functions called by the Inst* into the given
77 template <typename Inst>
78 static bool getPossibleTargets(Inst *, SmallVectorImpl<Function *> &);
168 void visitPtrToIntInst(PtrToIntInst &Inst) { argument
169 auto *Ptr = Inst.getOperand(0);
173 void visitIntToPtrInst(IntToPtrInst &Inst) { argument
174 auto *Ptr = &Inst;
178 void visitCastInst(CastInst &Inst) { argument
180 Edge(&Inst, Inst
183 visitBinaryOperator(BinaryOperator &Inst) argument
190 visitAtomicCmpXchgInst(AtomicCmpXchgInst &Inst) argument
196 visitAtomicRMWInst(AtomicRMWInst &Inst) argument
202 visitPHINode(PHINode &Inst) argument
208 visitGetElementPtrInst(GetElementPtrInst &Inst) argument
215 visitSelectInst(SelectInst &Inst) argument
229 visitLoadInst(LoadInst &Inst) argument
235 visitStoreInst(StoreInst &Inst) argument
241 visitVAArgInst(VAArgInst &Inst) argument
377 visitCallLikeInst(InstT &Inst) argument
400 visitCallInst(CallInst &Inst) argument
402 visitInvokeInst(InvokeInst &Inst) argument
409 visitExtractElementInst(ExtractElementInst &Inst) argument
415 visitInsertElementInst(InsertElementInst &Inst) argument
422 visitLandingPadInst(LandingPadInst &Inst) argument
429 visitInsertValueInst(InsertValueInst &Inst) argument
436 visitExtractValueInst(ExtractValueInst &Inst) argument
441 visitShuffleVectorInst(ShuffleVectorInst &Inst) argument
475 visitInstruction(Instruction &Inst) argument
477 visitStoreInst(StoreInst &Inst) argument
479 visitAtomicCmpXchgInst(AtomicCmpXchgInst &Inst) argument
483 visitAtomicRMWInst(AtomicRMWInst &Inst) argument
487 visitInsertElementInst(InsertElementInst &Inst) argument
491 visitInsertValueInst(InsertValueInst &Inst) argument
706 getTargetValue(Instruction *Inst) argument
711 hasUsefulEdges(Instruction *Inst) argument
755 argsToEdges(CFLAAResult &Analysis, Instruction *Inst, SmallVectorImpl<Edge> &Output) argument
812 addInstructionToGraph(CFLAAResult &Analysis, Instruction &Inst, SmallVectorImpl<Value *> &ReturnedValues, NodeMapT &Map, GraphT &Graph) argument
[all...]
H A DDelinearization.cpp73 static Value *getPointerOperand(Instruction &Inst) { argument
74 if (LoadInst *Load = dyn_cast<LoadInst>(&Inst))
76 else if (StoreInst *Store = dyn_cast<StoreInst>(&Inst))
78 else if (GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(&Inst))
86 Instruction *Inst = &(*I); local
89 if (!isa<StoreInst>(Inst) && !isa<LoadInst>(Inst) &&
90 !isa<GetElementPtrInst>(Inst))
93 const BasicBlock *BB = Inst->getParent();
97 const SCEV *AccessFn = SE->getSCEVAtScope(getPointerOperand(*Inst),
107 O << "Inst:" << *Inst << "\\n"; local
[all...]
H A DPHITransAddr.cpp25 static bool CanPHITrans(Instruction *Inst) { argument
26 if (isa<PHINode>(Inst) ||
27 isa<GetElementPtrInst>(Inst))
30 if (isa<CastInst>(Inst) &&
31 isSafeToSpeculativelyExecute(Inst))
34 if (Inst->getOpcode() == Instruction::Add &&
35 isa<ConstantInt>(Inst->getOperand(1)))
118 Instruction *Inst = dyn_cast<Instruction>(Addr); local
119 return !Inst || CanPHITrans(Inst);
149 Instruction *Inst = dyn_cast<Instruction>(V); local
[all...]
H A DMemDepPrinter.cpp100 Instruction *Inst = &I; local
102 if (!Inst->mayReadFromMemory() && !Inst->mayWriteToMemory())
105 MemDepResult Res = MDA.getDependency(Inst);
107 Deps[Inst].insert(std::make_pair(getInstTypePair(Res),
109 } else if (auto CS = CallSite(Inst)) {
113 DepSet &InstDeps = Deps[Inst];
121 assert( (isa<LoadInst>(Inst) || isa<StoreInst>(Inst) ||
122 isa<VAArgInst>(Inst))
139 const Instruction *Inst = &I; local
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
995 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1004 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1017 DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1028 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1039 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1050 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1061 DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1071 DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1078 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1090 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1102 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1113 DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1124 DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1135 DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1157 DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1178 DecodeLoadByte9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1196 DecodeLoadByte15(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1214 DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1231 DecodeCacheOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1248 DecodePrefeOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1265 DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1282 DecodeStoreEvaOpMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1300 DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1315 DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1330 DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1376 DecodeMemMMImm4(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1434 DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1450 DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1466 DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1491 DecodeMemMMImm9(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1512 DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1547 DecodeMemMMImm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1565 DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1583 DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1601 DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1619 DecodeFMemCop2R6(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1636 DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1658 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1669 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1682 DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1694 DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1706 DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1718 DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1730 DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1742 DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1754 DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1766 DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1778 DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1790 DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1802 DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1811 DecodeJumpTarget(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1821 DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1831 DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1841 DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1850 DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1859 DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1868 DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) argument
1878 DecodeJumpTargetMM(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1887 DecodeAddiur2Simm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1900 DecodeUImm6Lsl2(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1908 DecodeLiSimm7(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1919 DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1927 DecodeSimm4(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1935 DecodeSimm16(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1944 DecodeUImmWithOffset(MCInst &Inst, unsigned Value, uint64_t Address, const void *Decoder) argument
1952 DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1963 DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1969 DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1975 DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1989 DecodeANDI16Imm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigne
871 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
882 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
895 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
909 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
921 DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
936 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
966 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
991 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1012 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1027 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1035 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1050 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1070 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1091 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument
1103 DecodePredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1117 DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1126 DecodeSORegImmOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1163 DecodeSORegRegOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1198 DecodeRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1235 DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1259 DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1284 DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1311 DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1461 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1566 DecodeSORegMemOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
1610 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1801 DecodeRFEInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1830 DecodeQADDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1853 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1944 DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
1991 DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2033 DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2057 DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2084 DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2112 DecodeTSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2133 DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2161 DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2181 DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2200 DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2206 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2233 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2259 DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
2276 DecodeVLDInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2550 DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2563 DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2578 DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2591 DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2601 DecodeVSTInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2872 DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2919 DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
2967 DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3002 DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3055 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3100 DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3119 DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3125 DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3131 DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3137 DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3143 DecodeTBLInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3179 DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3203 DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3211 DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3219 DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3227 DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3242 DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3256 DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3266 DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3274 DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3302 DecodeT2LoadShift(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3384 DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3468 DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3548 DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3587 DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, uint64_t Address, const void* Decoder) argument
3640 DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3654 DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3669 DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, uint64_t Address, const void *Decoder) argument
3684 DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3697 DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3743 DecodeT2LdStPre(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3804 DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3830 DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3841 DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3866 DecodeThumbCPS(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) argument
3877 DecodePostIdxReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3890 DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3914 DecodeCoprocessor(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
3930 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3946 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
3988 DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4020 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4028 DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4051 DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4060 DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4069 DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4132 DecodeBankedReg(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
4155 DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4176 DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4201 DecodeLDRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4226 DecodeLDRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4254 DecodeSTRPreImm(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4279 DecodeSTRPreReg(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4304 DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4371 DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4437 DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4504 DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4568 DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4638 DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4702 DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4783 DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4855 DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4881 DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4907 DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4927 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4964 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
4998 DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument
5013 DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, uint64_t Address, const void *Decoder) argument
5024 DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5051 DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5110 DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
5169 DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
5196 DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Transforms/ObjCARC/
H A DDependencyAnalysis.h61 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
66 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
71 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
74 /// Returns true if we can not conservatively prove that Inst can not decrement
76 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr,
79 static inline bool CanDecrementRefCount(const Instruction *Inst, argument
82 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
H A DDependencyAnalysis.cpp35 bool llvm::objcarc::CanAlterRefCount(const Instruction *Inst, const Value *Ptr, argument
48 ImmutableCallSite CS(Inst);
56 const DataLayout &DL = Inst->getModule()->getDataLayout();
71 bool llvm::objcarc::CanDecrementRefCount(const Instruction *Inst, argument
80 return CanAlterRefCount(Inst, Ptr, PA, Class);
85 bool llvm::objcarc::CanUse(const Instruction *Inst, const Value *Ptr, argument
92 const DataLayout &DL = Inst->getModule()->getDataLayout();
96 if (const ICmpInst *ICI = dyn_cast<ICmpInst>(Inst)) {
102 } else if (auto CS = ImmutableCallSite(Inst)) {
112 } else if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
135 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg, ProvenanceAnalysis &PA) argument
255 Instruction *Inst = &*--LocalStartPos; local
[all...]
H A DObjCARCExpand.cpp98 Instruction *Inst = &*I; local
100 DEBUG(dbgs() << "ObjCARCExpand: Visiting: " << *Inst << "\n");
102 switch (GetBasicARCInstKind(Inst)) {
114 Value *Value = cast<CallInst>(Inst)->getArgOperand(0);
115 DEBUG(dbgs() << "ObjCARCExpand: Old = " << *Inst << "\n"
117 Inst->replaceAllUsesWith(Value);
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp33 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
36 static DecodeStatus DecodeFPR128_loRegisterClass(llvm::MCInst &Inst,
40 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeGPR64spRegisterClass(llvm::MCInst &Inst,
58 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
61 static DecodeStatus DecodeGPR32spRegisterClass(llvm::MCInst &Inst,
265 DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
276 DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
294 DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
315 DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
336 DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
357 DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
378 DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
389 DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
411 DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
422 DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
445 DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
467 DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
490 DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
513 DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
534 DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
557 DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
580 DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
590 DecodeFixedPointScaleImm32(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
599 DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
606 DecodePCRelLabel19(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
622 DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
629 DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
639 DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm, uint64_t Address, const void *Decoder) argument
647 DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) argument
670 DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
676 DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm, unsigned Add) argument
682 DecodeVecShiftR64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
687 DecodeVecShiftR64ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
693 DecodeVecShiftR32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
698 DecodeVecShiftR32ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
704 DecodeVecShiftR16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
709 DecodeVecShiftR16ImmNarrow(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
715 DecodeVecShiftR8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
720 DecodeVecShiftL64Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
725 DecodeVecShiftL32Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
730 DecodeVecShiftL16Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
735 DecodeVecShiftL8Imm(llvm::MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder) argument
740 DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
802 DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
835 DecodeUnsignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
896 DecodeSignedLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1081 DecodeExclusiveLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1164 DecodePairLdStInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1293 DecodeAddSubERegInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1350 DecodeLogicalImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1381 DecodeModImmInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1420 DecodeModImmTiedInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1438 DecodeAdrInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1457 DecodeBaseAddSubImm(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1493 DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1510 DecodeSystemPStateInstruction(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1535 DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, uint64_t Addr, const void *Decoder) argument
1559 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
1573 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
1582 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1673 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument
1676 Inst.addOperand(MCOperand::createImm(0));
1678 Inst
1683 addCondCodeOperands(MCInst &Inst, unsigned N) const argument
1690 addCoprocNumOperands(MCInst &Inst, unsigned N) const argument
1695 addCoprocRegOperands(MCInst &Inst, unsigned N) const argument
1700 addCoprocOptionOperands(MCInst &Inst, unsigned N) const argument
1705 addITMaskOperands(MCInst &Inst, unsigned N) const argument
1710 addITCondCodeOperands(MCInst &Inst, unsigned N) const argument
1715 addCCOutOperands(MCInst &Inst, unsigned N) const argument
1720 addRegOperands(MCInst &Inst, unsigned N) const argument
1725 addRegShiftedRegOperands(MCInst &Inst, unsigned N) const argument
1735 addRegShiftedImmOperands(MCInst &Inst, unsigned N) const argument
1746 addShifterImmOperands(MCInst &Inst, unsigned N) const argument
1752 addRegListOperands(MCInst &Inst, unsigned N) const argument
1760 addDPRRegListOperands(MCInst &Inst, unsigned N) const argument
1764 addSPRRegListOperands(MCInst &Inst, unsigned N) const argument
1768 addRotImmOperands(MCInst &Inst, unsigned N) const argument
1774 addModImmOperands(MCInst &Inst, unsigned N) const argument
1784 addModImmNotOperands(MCInst &Inst, unsigned N) const argument
1791 addModImmNegOperands(MCInst &Inst, unsigned N) const argument
1798 addBitfieldOperands(MCInst &Inst, unsigned N) const argument
1809 addImmOperands(MCInst &Inst, unsigned N) const argument
1814 addFBits16Operands(MCInst &Inst, unsigned N) const argument
1820 addFBits32Operands(MCInst &Inst, unsigned N) const argument
1826 addFPImmOperands(MCInst &Inst, unsigned N) const argument
1833 addImm8s4Operands(MCInst &Inst, unsigned N) const argument
1841 addImm0_1020s4Operands(MCInst &Inst, unsigned N) const argument
1849 addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const argument
1857 addImm0_508s4Operands(MCInst &Inst, unsigned N) const argument
1865 addImm1_16Operands(MCInst &Inst, unsigned N) const argument
1873 addImm1_32Operands(MCInst &Inst, unsigned N) const argument
1881 addImmThumbSROperands(MCInst &Inst, unsigned N) const argument
1890 addPKHASRImmOperands(MCInst &Inst, unsigned N) const argument
1899 addT2SOImmNotOperands(MCInst &Inst, unsigned N) const argument
1907 addT2SOImmNegOperands(MCInst &Inst, unsigned N) const argument
1915 addImm0_4095NegOperands(MCInst &Inst, unsigned N) const argument
1923 addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const argument
1934 addThumbMemPCOperands(MCInst &Inst, unsigned N) const argument
1954 addMemBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1959 addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const argument
1964 addMemNoOffsetOperands(MCInst &Inst, unsigned N) const argument
1969 addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const argument
1975 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument
1991 addAlignedMemoryOperands(MCInst &Inst, unsigned N) const argument
1997 addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2001 addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const argument
2005 addAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2009 addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const argument
2013 addAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2017 addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const argument
2021 addAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2025 addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const argument
2029 addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2033 addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const argument
2037 addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const argument
2041 addAddrMode2Operands(MCInst &Inst, unsigned N) const argument
2259 addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const argument
2266 addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const argument
2273 addMemThumbSPIOperands(MCInst &Inst, unsigned N) const argument
2280 addPostIdxImm8Operands(MCInst &Inst, unsigned N) const argument
2291 addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const argument
2303 addPostIdxRegOperands(MCInst &Inst, unsigned N) const argument
2309 addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const argument
2320 addMSRMaskOperands(MCInst &Inst, unsigned N) const argument
2325 addBankedRegOperands(MCInst &Inst, unsigned N) const argument
2330 addProcIFlagsOperands(MCInst &Inst, unsigned N) const argument
2335 addVecListOperands(MCInst &Inst, unsigned N) const argument
2340 addVecListIndexedOperands(MCInst &Inst, unsigned N) const argument
2346 addVectorIndex8Operands(MCInst &Inst, unsigned N) const argument
2351 addVectorIndex16Operands(MCInst &Inst, unsigned N) const argument
2356 addVectorIndex32Operands(MCInst &Inst, unsigned N) const argument
2361 addNEONi8splatOperands(MCInst &Inst, unsigned N) const argument
2369 addNEONi16splatOperands(MCInst &Inst, unsigned N) const argument
2378 addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const argument
2387 addNEONi32splatOperands(MCInst &Inst, unsigned N) const argument
2396 addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const argument
2405 addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2418 addNEONi32vmovOperands(MCInst &Inst, unsigned N) const argument
2432 addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const argument
2445 addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const argument
2459 addNEONi64splatOperands(MCInst &Inst, unsigned N) const argument
4618 cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) argument
4634 cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) argument
5643 RequiresVFPRegListValidation(StringRef Inst, bool &AcceptSinglePrecisionOnly, bool &AcceptDoublePrecisionOnly) argument
5962 checkLowRegisterList(const MCInst &Inst, unsigned OpNo, unsigned Reg, unsigned HiReg, bool &containsReg) argument
5979 listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) argument
5990 instIsBreakpoint(const MCInst &Inst) argument
5998 validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo, bool IsARPop) argument
6021 validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo) argument
6043 validateInstruction(MCInst &Inst, const OperandVector &Operands) argument
6669 processInstruction(MCInst &Inst, const OperandVector &Operands, MCStreamer &Out) argument
8511 checkTargetMatchPredicate(MCInst &Inst) argument
8575 MCInst Inst; local
[all...]
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DInstrInfoEmitter.cpp55 void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
71 std::vector<std::string> GetOperandInfo(const CodeGenInstruction &Inst);
88 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { argument
91 for (auto &Op : Inst.Operands) {
180 for (const CodeGenInstruction *Inst : Target.instructions()) {
181 std::vector<std::string> OperandInfo = GetOperandInfo(*Inst);
207 for (const CodeGenInstruction *Inst : NumberedInstructions) {
208 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
211 for (const auto &Info : Inst->Operands) {
220 OperandMap[OpList].push_back(Namespace + "::" + Inst
362 Record *Inst = II->TheDef; local
462 emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) argument
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp651 inline static void addOps(MCInst &subInstPtr, MCInst const &Inst, argument
653 if (Inst.getOperand(opNum).isReg()) {
654 switch (Inst.getOperand(opNum).getReg()) {
682 subInstPtr.addOperand(Inst.getOperand(opNum));
686 subInstPtr.addOperand(Inst.getOperand(opNum));
689 MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { argument
693 switch (Inst.getOpcode()) {
695 // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
699 Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
703 addOps(Result, Inst,
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h19 struct Inst { struct in class:llvm::MipsAnalyzeImmediate
21 Inst(unsigned Opc, unsigned ImmOpnd);
23 typedef SmallVector<Inst, 7 > InstSeq;
33 void AddInstr(InstSeqLs &SeqLs, const Inst &I);
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp119 int processInstruction(MCInst &Inst, OperandVector const &Operands,
352 void addRegOperands(MCInst &Inst, unsigned N) const { argument
354 Inst.addOperand(MCOperand::createReg(getReg()));
357 void addImmOperands(MCInst &Inst, unsigned N) const { argument
359 Inst.addOperand(MCOperand::createExpr(getImm()));
362 void addSignedImmOperands(MCInst &Inst, unsigned N) const { argument
367 Inst.addOperand(MCOperand::createExpr(Expr));
372 Inst.addOperand(MCOperand::createExpr(Expr));
377 Inst.addOperand(MCOperand::createImm(Extended));
380 void addf32ExtOperands(MCInst &Inst, unsigne argument
384 adds32ImmOperands(MCInst &Inst, unsigned N) const argument
387 adds8ImmOperands(MCInst &Inst, unsigned N) const argument
390 adds8Imm64Operands(MCInst &Inst, unsigned N) const argument
393 adds6ImmOperands(MCInst &Inst, unsigned N) const argument
396 adds4ImmOperands(MCInst &Inst, unsigned N) const argument
399 adds4_0ImmOperands(MCInst &Inst, unsigned N) const argument
402 adds4_1ImmOperands(MCInst &Inst, unsigned N) const argument
405 adds4_2ImmOperands(MCInst &Inst, unsigned N) const argument
408 adds4_3ImmOperands(MCInst &Inst, unsigned N) const argument
411 adds3ImmOperands(MCInst &Inst, unsigned N) const argument
415 addu64ImmOperands(MCInst &Inst, unsigned N) const argument
418 addu32ImmOperands(MCInst &Inst, unsigned N) const argument
421 addu26_6ImmOperands(MCInst &Inst, unsigned N) const argument
424 addu16ImmOperands(MCInst &Inst, unsigned N) const argument
427 addu16_0ImmOperands(MCInst &Inst, unsigned N) const argument
430 addu16_1ImmOperands(MCInst &Inst, unsigned N) const argument
433 addu16_2ImmOperands(MCInst &Inst, unsigned N) const argument
436 addu16_3ImmOperands(MCInst &Inst, unsigned N) const argument
439 addu11_3ImmOperands(MCInst &Inst, unsigned N) const argument
442 addu10ImmOperands(MCInst &Inst, unsigned N) const argument
445 addu9ImmOperands(MCInst &Inst, unsigned N) const argument
448 addu8ImmOperands(MCInst &Inst, unsigned N) const argument
451 addu7ImmOperands(MCInst &Inst, unsigned N) const argument
454 addu6ImmOperands(MCInst &Inst, unsigned N) const argument
457 addu6_0ImmOperands(MCInst &Inst, unsigned N) const argument
460 addu6_1ImmOperands(MCInst &Inst, unsigned N) const argument
463 addu6_2ImmOperands(MCInst &Inst, unsigned N) const argument
466 addu6_3ImmOperands(MCInst &Inst, unsigned N) const argument
469 addu5ImmOperands(MCInst &Inst, unsigned N) const argument
472 addu4ImmOperands(MCInst &Inst, unsigned N) const argument
475 addu3ImmOperands(MCInst &Inst, unsigned N) const argument
478 addu2ImmOperands(MCInst &Inst, unsigned N) const argument
481 addu1ImmOperands(MCInst &Inst, unsigned N) const argument
485 addm6ImmOperands(MCInst &Inst, unsigned N) const argument
488 addn8ImmOperands(MCInst &Inst, unsigned N) const argument
492 adds16ExtOperands(MCInst &Inst, unsigned N) const argument
495 adds12ExtOperands(MCInst &Inst, unsigned N) const argument
498 adds10ExtOperands(MCInst &Inst, unsigned N) const argument
501 adds9ExtOperands(MCInst &Inst, unsigned N) const argument
504 adds8ExtOperands(MCInst &Inst, unsigned N) const argument
507 adds6ExtOperands(MCInst &Inst, unsigned N) const argument
510 adds11_0ExtOperands(MCInst &Inst, unsigned N) const argument
513 adds11_1ExtOperands(MCInst &Inst, unsigned N) const argument
516 adds11_2ExtOperands(MCInst &Inst, unsigned N) const argument
519 adds11_3ExtOperands(MCInst &Inst, unsigned N) const argument
523 addu6ExtOperands(MCInst &Inst, unsigned N) const argument
526 addu7ExtOperands(MCInst &Inst, unsigned N) const argument
529 addu8ExtOperands(MCInst &Inst, unsigned N) const argument
532 addu9ExtOperands(MCInst &Inst, unsigned N) const argument
535 addu10ExtOperands(MCInst &Inst, unsigned N) const argument
538 addu6_0ExtOperands(MCInst &Inst, unsigned N) const argument
541 addu6_1ExtOperands(MCInst &Inst, unsigned N) const argument
544 addu6_2ExtOperands(MCInst &Inst, unsigned N) const argument
547 addu6_3ExtOperands(MCInst &Inst, unsigned N) const argument
550 addu32MustExtOperands(MCInst &Inst, unsigned N) const argument
554 adds4_6ImmOperands(MCInst &Inst, unsigned N) const argument
560 adds3_6ImmOperands(MCInst &Inst, unsigned N) const argument
1525 processInstruction(MCInst &Inst, OperandVector const &Operands, SMLoc IDLoc, bool &MustExtend) argument
[all...]

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