Searched refs:DstRC (Results 1 - 16 of 16) sorted by relevance

/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp143 const TargetRegisterClass *DstRC = local
148 return std::make_pair(SrcRC, DstRC);
152 const TargetRegisterClass *DstRC,
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
158 const TargetRegisterClass *DstRC,
160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC);
193 const TargetRegisterClass *SrcRC, *DstRC; local
194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI);
196 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI))
204 MRI.setRegClass(DstReg, DstRC);
151 isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
157 isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const SIRegisterInfo &TRI) argument
265 const TargetRegisterClass *SrcRC, *DstRC; local
357 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; local
[all...]
H A DSILowerI1Copies.cpp107 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); local
110 if (DstRC == &AMDGPU::VReg_1RegClass &&
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
H A DSIInstrInfo.cpp493 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
495 if (DstRC->getSize() == 4) {
496 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
497 } else if (DstRC->getSize() == 8 && RI.isSGPRClass(DstRC)) {
499 } else if (DstRC->getSize() == 8 && !RI.isSGPRClass(DstRC)) {
2035 const TargetRegisterClass *DstRC = getOpRegClass(*MI, 0);
2036 if (RI.hasVGPRs(DstRC)) {
2068 const TargetRegisterClass *DstRC
[all...]
H A DSIInstrInfo.h124 // \brief Returns an opcode that can be used to move a value to a \p DstRC
126 // DstRC, then AMDGPU::COPY is returned.
127 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp132 const TargetRegisterClass *DstRC = local
142 unsigned NewVReg = MRI.createVirtualRegister(DstRC);
H A DPPCVSXSwapRemoval.cpp855 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
856 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
869 if (DstRC == &PPC::VRRCRegClass) {
/freebsd-11.0-release/contrib/llvm/utils/TableGen/
H A DFastISelEmitter.cpp193 const CodeGenRegisterClass *DstRC = nullptr;
275 if (DstRC) {
276 if (DstRC != RC && !DstRC->hasSubClass(RC))
279 DstRC = RC;
481 const CodeGenRegisterClass *DstRC = nullptr;
489 DstRC = &Target.getRegisterClass(Op0Rec);
490 if (!DstRC)
529 DstRC))
580 DstRC,
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; local
161 DstRC = MRI->getRegClass(VRBase);
164 DstRC = UseRC;
166 DstRC = TLI->getRegClassFor(VT);
175 VRBase = MRI->createVirtualRegister(DstRC);
333 const TargetRegisterClass *DstRC = nullptr;
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
[all...]
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h189 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
193 const TargetRegisterClass *DstRC,
H A DARMBaseRegisterInfo.cpp781 const TargetRegisterClass *DstRC,
792 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
800 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
778 shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC) const argument
H A DARMFastISel.cpp2043 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); local
2044 unsigned ResultReg = createResultReg(DstRC);
2063 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); local
2065 unsigned ResultReg = createResultReg(DstRC);
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DRegisterCoalescer.cpp343 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); local
351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
380 CrossClass = NewRC != DstRC || NewRC != SrcRC;
959 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
961 TRI->getCommonSubClass(DefRC, DstRC);
1280 auto DstRC = MRI->getRegClass(CP.getDstReg()); local
1285 std::swap(SrcRC, DstRC);
[all...]
H A DPeepholeOptimizer.cpp428 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); local
429 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
430 if (!DstRC)
536 MRI->constrainRegClass(DstReg, DstRC);
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp641 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
645 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC))
648 if (DstRC != SrcRC)
650 if (DstRC == InsRC)
653 if (DstRC == &Hexagon::DoubleRegsRegClass)
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h869 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true.
873 const TargetRegisterClass *DstRC,
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp6250 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); local
6255 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
6324 const TargetRegisterClass *DstRC = nullptr; local
6326 DstRC = getRegClass(MCID, 0, &RI, MF);
6327 VTs.push_back(*DstRC->vt_begin());
6360 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),

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