Searched refs:D7 (Results 1 - 16 of 16) sorted by relevance
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.h | 39 AArch64::D6, AArch64::D7};
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H A D | AArch64PBQPRegAlloc.cpp | 67 case AArch64::D7:
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H A D | AArch64FastISel.cpp | 2857 AArch64::D5, AArch64::D6, AArch64::D7 },
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 65 case D7: case D6: case D5: case D4:
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H A D | ARMCallingConv.h | 170 ARM::D4, ARM::D5, ARM::D6, ARM::D7 };
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/freebsd-11.0-release/lib/msun/ld128/ |
H A D | s_expl.c | 177 D7 = 1.98412698412698412699085805424661471e-4L, variable 252 x * (D7 + x * (D8 + x * (D9 + x * (D10 +
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/freebsd-11.0-release/crypto/openssl/crypto/ec/asm/ |
H A D | ecp_nistz256-avx2.pl | 307 my ($D0,$D1,$D2,$D3, $D4,$D5,$D6,$D7, $D8)=map("%ymm$_",(0..8)); 343 vmovdqa 32*7-160(%rax), $D7 364 vpsllq \$11, $D7, $D7 366 vpaddq $D6, $D7, $D7 367 vpaddq $D7, $T3, $D3 # out[3] = (in[6] >> (64*3-shift*6)) ^ (in[7] << shift*7%64) ^ (in[8] << shift*8%64);
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 119 case AArch64::D7: return AArch64::B7; 159 case AArch64::B7: return AArch64::D7;
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 123 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7, 124 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 91 SP::D6, SP::D22, SP::D7, SP::D23,
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/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.cpp | 49 MAP(D7, 55) \
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/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 524 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 286 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1106 VA.convertToReg(Mips::D7);
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H A D | MipsISelLowering.cpp | 2446 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1003 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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