Searched refs:D15 (Results 1 - 12 of 12) sorted by relevance
| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 63 case D15: case D14: case D13: case D12:
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| /freebsd-11.0-release/lib/msun/ld128/ |
| H A D | s_expl.c | 194 D15 = 7.6478532249581686e-13, /* 0x1.ae892e3D16fcep-41 */ variable
254 dx * (D14 + dx * (D15 + dx * (D16 +
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 108 Reserved.set(Hexagon::D15);
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| H A D | HexagonFrameLowering.cpp | 197 if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
681 if (Reg < Hexagon::D0 || Reg > Hexagon::D15) {
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 71 case AArch64::D15:
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AsmBackend.cpp | 413 // D14/D15 pair = 0x00000800
423 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 127 case AArch64::D15: return AArch64::B15;
167 case AArch64::B15: return AArch64::D15;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 95 SP::D14, SP::D30, SP::D15, SP::D31 };
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 125 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 526 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
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| /freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 288 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1005 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
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