Searched refs:x1 (Results 1 - 25 of 1815) sorted by relevance

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/freebsd-11-stable/lib/msun/src/
H A Ds_exp2.c39 redux = 0x1.8p52 / TBLSIZE,
40 P1 = 0x1.62e42fefa39efp-1,
41 P2 = 0x1.ebfbdff82c575p-3,
42 P3 = 0x1.c6b08d704a0a6p-5,
43 P4 = 0x1.3b2ab88f70400p-7,
44 P5 = 0x1.5d88003875c74p-10;
52 0x1.6a09e667f3d5dp-1, 0x1.9880p-44,
53 0x1.6b052fa751744p-1, 0x1
[all...]
H A Ds_exp2f.c39 redux = 0x1.8p23f / TBLSIZE,
40 P1 = 0x1.62e430p-1f,
41 P2 = 0x1.ebfbe0p-3f,
42 P3 = 0x1.c6b348p-5f,
43 P4 = 0x1.3b2c9cp-7f;
50 0x1.6a09e667f3bcdp-1,
51 0x1.7a11473eb0187p-1,
52 0x1.8ace5422aa0dbp-1,
53 0x1.9c49182a3f090p-1,
54 0x1
[all...]
/freebsd-11-stable/lib/msun/ld128/
H A Ds_exp2l.c47 P1 = 0x1.62e42fefa39ef35793c7673007e6p-1L,
48 P2 = 0x1.ebfbdff82c58ea86f16b06ec9736p-3L,
49 P3 = 0x1.c6b08d704a0bf8b33a762bad3459p-5L,
50 P4 = 0x1.3b2ab6fba4e7729ccbbe0b4f3fc2p-7L,
51 P5 = 0x1.5d87fe78a67311071dee13fd11d9p-10L,
52 P6 = 0x1.430912f86c7876f4b663b23c5fe5p-13L;
55 P7 = 0x1.ffcbfc588b041p-17,
56 P8 = 0x1.62c0223a5c7c7p-20,
57 P9 = 0x1.b52541ff59713p-24,
58 P10 = 0x1
[all...]
H A Dk_expl.h52 L2 = -1.0253670638894731e-29; /* -0x1.9ff0342542fc3p-97 */
54 /* 0x1.62e42fefa39ef35793c768000000p-8 */
76 A7 = 1.9841269841269470e-4, /* 0x1.a01a01a019f91p-13 */
77 A8 = 2.4801587301585286e-5, /* 0x1.71de3ec75a967p-19 */
78 A9 = 2.7557324277411235e-6, /* 0x1.71de3ec75a967p-19 */
79 A10 = 2.7557333722375069e-7; /* 0x1.27e505ab56259p-22 */
103 0x1.0163da9fb33356d84a66aep0L, 0x3.36dcdfa4003ec04c360be2404078p-92L,
104 0x1.02c9a3e778060ee6f7cacap0L, 0x4.f7a29bde93d70a2cabc5cb89ba10p-92L,
105 0x1.04315e86e7f84bd738f9a2p0L, 0xd.a47e6ed040bb4bfc05af6455e9b8p-96L,
106 0x1
[all...]
/freebsd-11-stable/lib/msun/ld80/
H A Dk_expl.h81 * But I rather like both. The 0x1.*p format is good for 4N+1
85 { 0x1.0163da9fb3335p+0, 0x1.b61299ab8cdb7p-54 },
86 { 0x1.02c9a3e778060p+0, 0x1.dcdef95949ef4p-53 },
87 { 0x1.04315e86e7f84p+0, 0x1.7ae71f3441b49p-53 },
88 { 0x1.059b0d3158574p+0, 0x1.d73e2a475b465p-55 },
89 { 0x1
[all...]
H A Ds_exp2l.c54 redux = 0x1.8p63 / TBLSIZE,
66 0x1.6a09e667f3bcdp-1, -0x1.bdd3413b2648p-55,
67 0x1.6c012750bdabfp-1, -0x1.2895667ff0cp-57,
68 0x1.6dfb23c651a2fp-1, -0x1.bbe3a683c88p-58,
69 0x1.6ff7df9519484p-1, -0x1.83c0f25860fp-56,
70 0x1
[all...]
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_tx99_tgt.c172 | (0x1 << 3) | (0x1 << 2));
175 & ~(0x1 << 4));
177 | (0x1 << 26) | (0x7 << 24))
178 & ~(0x1 << 22));
181 & ~(0x1 << 4));
183 | (0x1 << 26) | (0x7 << 24))
184 & ~(0x1 << 22));
190 | (0x1 << 31) | (0x5 << 15)
191 | (0x3 << 9)) & ~(0x1 << 2
[all...]
/freebsd-11-stable/sys/dev/qlnx/qlnxe/
H A Decore_hw_defs.h35 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
36 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
37 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
38 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
39 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
40 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
43 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
44 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
45 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
67 #define IGU_CTRL_REG_RESERVED_MASK 0x1
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H A Decore_hsi_fcoe.h63 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */
65 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */
73 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
75 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
90 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
154 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */
156 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */
158 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */
160 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */
162 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 /* Indicaito
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H A Dreg_addr.h35 #define PGLCS_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
37 #define PGLCS_REG_INT_STS_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
40 #define PGLCS_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
42 #define PGLCS_REG_INT_MASK_RASDP_ERROR_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
45 #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
47 #define PGLCS_REG_INT_STS_WR_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
50 #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module.
52 #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR_K2_E5 (0x1<<1) // It indicates rasdp error
54 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF_K2_E5 0x001d10UL //Access:RW DataWidth:0x1 // Disable rasdp error mode check
100 #define PCIEIP_REG_PCIEEP_CMD_ISAE_E5 (0x1<<
[all...]
H A Decore_hsi_iscsi.h75 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
77 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 /* exist_in_qm1 */
79 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm2 */
81 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
83 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */
85 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 /* cf_array_active */
87 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */
89 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */
92 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */
94 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 /* bit
[all...]
H A Decore_hsi_rdma.h54 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
56 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */
58 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */
60 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */
69 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */
71 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */
74 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */
76 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */
78 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */
80 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2e
[all...]
H A Decore_hsi_roce.h142 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
144 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
148 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
193 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
195 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
197 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
199 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
201 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
203 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
209 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
[all...]
H A Decore_hsi_eth.h67 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */
69 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */
71 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */
73 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */
75 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */
77 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */
79 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */
81 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */
84 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */
86 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit
[all...]
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Drv250d.h38 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3)
39 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1)
41 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4)
42 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1)
44 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5)
45 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1)
47 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6)
48 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1)
50 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7)
51 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1)
[all...]
H A Dr100d.h83 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
84 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
86 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
87 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
89 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2)
90 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1)
92 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
93 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
95 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
96 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
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H A Drs600d.h36 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
37 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
39 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
40 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
42 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
43 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
45 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
46 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
48 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
49 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
[all...]
H A Dr520d.h44 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
45 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
47 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
48 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
50 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
51 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
53 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
54 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
56 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
57 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
[all...]
H A Drv350d.h36 #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21)
37 #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1)
39 #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25)
40 #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1)
42 #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26)
43 #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1)
45 #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27)
46 #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1)
48 #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28)
49 #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1)
[all...]
H A Dr420d.h38 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8)
39 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1)
46 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
47 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
49 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
50 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
52 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
53 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
55 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
56 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
[all...]
H A Drs400d.h50 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
51 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
53 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
54 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
56 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
57 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
59 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
60 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
62 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
63 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
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H A Drs690d.h39 #define S_000078_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
40 #define G_000078_MC_IND_WR_EN(x) (((x) >> 9) & 0x1)
55 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
56 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
58 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
59 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
61 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
62 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
64 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
65 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
[all...]
H A Dr300d.h106 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
107 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
109 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
110 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
112 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
113 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
115 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
116 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
118 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
119 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
[all...]
/freebsd-11-stable/contrib/binutils/opcodes/
H A Dia64-asmtab.c1938 { 0x1, 0x1, 0, -1, -1, 13, 1, 0 },
2026 { 0x1, 0x1, 0, 1166, -1, 20, 1, 68 },
2095 { 0x1, 0x1, 0, -1, -1, 13, 1, 0 },
2139 { 0x1, 0x1, 2, -1, -1, 27, 1, 12 },
2140 { 0x1, 0x1,
[all...]
/freebsd-11-stable/sys/gnu/dts/include/dt-bindings/phy/
H A Dphy-pistachio-usb.h13 #define REFCLK_X0_EXT_CLK 0x1

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