1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell#ifndef __R100D_H__ 29254885Sdumbbell#define __R100D_H__ 30254885Sdumbbell 31254885Sdumbbell#include <sys/cdefs.h> 32254885Sdumbbell__FBSDID("$FreeBSD$"); 33254885Sdumbbell 34254885Sdumbbell#define CP_PACKET0 0x00000000 35254885Sdumbbell#define PACKET0_BASE_INDEX_SHIFT 0 36254885Sdumbbell#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 37254885Sdumbbell#define PACKET0_COUNT_SHIFT 16 38254885Sdumbbell#define PACKET0_COUNT_MASK (0x3fff << 16) 39254885Sdumbbell#define CP_PACKET1 0x40000000 40254885Sdumbbell#define CP_PACKET2 0x80000000 41254885Sdumbbell#define PACKET2_PAD_SHIFT 0 42254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 43254885Sdumbbell#define CP_PACKET3 0xC0000000 44254885Sdumbbell#define PACKET3_IT_OPCODE_SHIFT 8 45254885Sdumbbell#define PACKET3_IT_OPCODE_MASK (0xff << 8) 46254885Sdumbbell#define PACKET3_COUNT_SHIFT 16 47254885Sdumbbell#define PACKET3_COUNT_MASK (0x3fff << 16) 48254885Sdumbbell/* PACKET3 op code */ 49254885Sdumbbell#define PACKET3_NOP 0x10 50254885Sdumbbell#define PACKET3_3D_DRAW_VBUF 0x28 51254885Sdumbbell#define PACKET3_3D_DRAW_IMMD 0x29 52254885Sdumbbell#define PACKET3_3D_DRAW_INDX 0x2A 53254885Sdumbbell#define PACKET3_3D_LOAD_VBPNTR 0x2F 54254885Sdumbbell#define PACKET3_3D_CLEAR_ZMASK 0x32 55254885Sdumbbell#define PACKET3_INDX_BUFFER 0x33 56254885Sdumbbell#define PACKET3_3D_DRAW_VBUF_2 0x34 57254885Sdumbbell#define PACKET3_3D_DRAW_IMMD_2 0x35 58254885Sdumbbell#define PACKET3_3D_DRAW_INDX_2 0x36 59254885Sdumbbell#define PACKET3_3D_CLEAR_HIZ 0x37 60254885Sdumbbell#define PACKET3_BITBLT_MULTI 0x9B 61254885Sdumbbell 62254885Sdumbbell#define PACKET0(reg, n) (CP_PACKET0 | \ 63254885Sdumbbell REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 64254885Sdumbbell REG_SET(PACKET0_COUNT, (n))) 65254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 66254885Sdumbbell#define PACKET3(op, n) (CP_PACKET3 | \ 67254885Sdumbbell REG_SET(PACKET3_IT_OPCODE, (op)) | \ 68254885Sdumbbell REG_SET(PACKET3_COUNT, (n))) 69254885Sdumbbell 70254885Sdumbbell#define PACKET_TYPE0 0 71254885Sdumbbell#define PACKET_TYPE1 1 72254885Sdumbbell#define PACKET_TYPE2 2 73254885Sdumbbell#define PACKET_TYPE3 3 74254885Sdumbbell 75254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 76254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 77254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 78254885Sdumbbell#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 79254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 80254885Sdumbbell 81254885Sdumbbell/* Registers */ 82254885Sdumbbell#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 83254885Sdumbbell#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 84254885Sdumbbell#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 85254885Sdumbbell#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 86254885Sdumbbell#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 87254885Sdumbbell#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 88254885Sdumbbell#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 89254885Sdumbbell#define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 90254885Sdumbbell#define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 91254885Sdumbbell#define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 92254885Sdumbbell#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 93254885Sdumbbell#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 94254885Sdumbbell#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 95254885Sdumbbell#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 96254885Sdumbbell#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 97254885Sdumbbell#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 98254885Sdumbbell#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 99254885Sdumbbell#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 100254885Sdumbbell#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 101254885Sdumbbell#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 102254885Sdumbbell#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 103254885Sdumbbell#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 104254885Sdumbbell#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 105254885Sdumbbell#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 106254885Sdumbbell#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 107254885Sdumbbell#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 108254885Sdumbbell#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 109254885Sdumbbell#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 110254885Sdumbbell#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 111254885Sdumbbell#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 112254885Sdumbbell#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 113254885Sdumbbell#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 114254885Sdumbbell#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 115254885Sdumbbell#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 116254885Sdumbbell#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 117254885Sdumbbell#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 118254885Sdumbbell#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 119254885Sdumbbell#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 120254885Sdumbbell#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 121254885Sdumbbell#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 122254885Sdumbbell#define R_000030_BUS_CNTL 0x000030 123254885Sdumbbell#define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 124254885Sdumbbell#define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 125254885Sdumbbell#define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 126254885Sdumbbell#define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 127254885Sdumbbell#define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 128254885Sdumbbell#define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 129254885Sdumbbell#define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 130254885Sdumbbell#define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 131254885Sdumbbell#define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 132254885Sdumbbell#define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 133254885Sdumbbell#define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 134254885Sdumbbell#define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 135254885Sdumbbell#define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 136254885Sdumbbell#define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 137254885Sdumbbell#define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 138254885Sdumbbell#define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 139254885Sdumbbell#define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 140254885Sdumbbell#define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 141254885Sdumbbell#define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 142254885Sdumbbell#define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 143254885Sdumbbell#define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 144254885Sdumbbell#define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 145254885Sdumbbell#define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 146254885Sdumbbell#define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 147254885Sdumbbell#define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 148254885Sdumbbell#define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 149254885Sdumbbell#define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 150254885Sdumbbell#define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 151254885Sdumbbell#define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 152254885Sdumbbell#define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 153254885Sdumbbell#define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 154254885Sdumbbell#define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 155254885Sdumbbell#define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 156254885Sdumbbell#define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 157254885Sdumbbell#define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 158254885Sdumbbell#define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 159254885Sdumbbell#define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 160254885Sdumbbell#define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 161254885Sdumbbell#define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 162254885Sdumbbell#define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 163254885Sdumbbell#define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 164254885Sdumbbell#define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 165254885Sdumbbell#define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 166254885Sdumbbell#define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 167254885Sdumbbell#define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 168254885Sdumbbell#define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 169254885Sdumbbell#define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 170254885Sdumbbell#define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 171254885Sdumbbell#define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 172254885Sdumbbell#define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 173254885Sdumbbell#define C_000030_BUS_RETRY_WS 0xFFF0FFFF 174254885Sdumbbell#define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 175254885Sdumbbell#define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 176254885Sdumbbell#define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 177254885Sdumbbell#define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 178254885Sdumbbell#define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 179254885Sdumbbell#define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 180254885Sdumbbell#define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 181254885Sdumbbell#define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 182254885Sdumbbell#define C_000030_BUS_SUSPEND 0xFFBFFFFF 183254885Sdumbbell#define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 184254885Sdumbbell#define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 185254885Sdumbbell#define C_000030_LAT_16X 0xFF7FFFFF 186254885Sdumbbell#define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 187254885Sdumbbell#define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 188254885Sdumbbell#define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 189254885Sdumbbell#define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 190254885Sdumbbell#define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 191254885Sdumbbell#define C_000030_ENFRCWRDY 0xFDFFFFFF 192254885Sdumbbell#define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 193254885Sdumbbell#define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 194254885Sdumbbell#define C_000030_BUS_MSTR_WS 0xFBFFFFFF 195254885Sdumbbell#define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 196254885Sdumbbell#define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 197254885Sdumbbell#define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 198254885Sdumbbell#define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 199254885Sdumbbell#define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 200254885Sdumbbell#define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 201254885Sdumbbell#define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 202254885Sdumbbell#define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 203254885Sdumbbell#define C_000030_SERR_EN 0xDFFFFFFF 204254885Sdumbbell#define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 205254885Sdumbbell#define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 206254885Sdumbbell#define C_000030_BUS_READ_BURST 0xBFFFFFFF 207254885Sdumbbell#define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 208254885Sdumbbell#define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 209254885Sdumbbell#define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 210254885Sdumbbell#define R_000040_GEN_INT_CNTL 0x000040 211254885Sdumbbell#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 212254885Sdumbbell#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 213254885Sdumbbell#define C_000040_CRTC_VBLANK 0xFFFFFFFE 214254885Sdumbbell#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 215254885Sdumbbell#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 216254885Sdumbbell#define C_000040_CRTC_VLINE 0xFFFFFFFD 217254885Sdumbbell#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 218254885Sdumbbell#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 219254885Sdumbbell#define C_000040_CRTC_VSYNC 0xFFFFFFFB 220254885Sdumbbell#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 221254885Sdumbbell#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 222254885Sdumbbell#define C_000040_SNAPSHOT 0xFFFFFFF7 223254885Sdumbbell#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 224254885Sdumbbell#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 225254885Sdumbbell#define C_000040_FP_DETECT 0xFFFFFFEF 226254885Sdumbbell#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 227254885Sdumbbell#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 228254885Sdumbbell#define C_000040_CRTC2_VLINE 0xFFFFFFDF 229254885Sdumbbell#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 230254885Sdumbbell#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 231254885Sdumbbell#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 232254885Sdumbbell#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 233254885Sdumbbell#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 234254885Sdumbbell#define C_000040_CRTC2_VSYNC 0xFFFFFFBF 235254885Sdumbbell#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 236254885Sdumbbell#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 237254885Sdumbbell#define C_000040_SNAPSHOT2 0xFFFFFF7F 238254885Sdumbbell#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 239254885Sdumbbell#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 240254885Sdumbbell#define C_000040_CRTC2_VBLANK 0xFFFFFDFF 241254885Sdumbbell#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 242254885Sdumbbell#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 243254885Sdumbbell#define C_000040_FP2_DETECT 0xFFFFFBFF 244254885Sdumbbell#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 245254885Sdumbbell#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 246254885Sdumbbell#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 247254885Sdumbbell#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 248254885Sdumbbell#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 249254885Sdumbbell#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 250254885Sdumbbell#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 251254885Sdumbbell#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 252254885Sdumbbell#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 253254885Sdumbbell#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 254254885Sdumbbell#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 255254885Sdumbbell#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 256254885Sdumbbell#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 257254885Sdumbbell#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 258254885Sdumbbell#define C_000040_I2C_INT_EN 0xFFFDFFFF 259254885Sdumbbell#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 260254885Sdumbbell#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 261254885Sdumbbell#define C_000040_GUI_IDLE 0xFFF7FFFF 262254885Sdumbbell#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 263254885Sdumbbell#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 264254885Sdumbbell#define C_000040_VIPH_INT_EN 0xFEFFFFFF 265254885Sdumbbell#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 266254885Sdumbbell#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 267254885Sdumbbell#define C_000040_SW_INT_EN 0xFDFFFFFF 268254885Sdumbbell#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 269254885Sdumbbell#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 270254885Sdumbbell#define C_000040_GEYSERVILLE 0xF7FFFFFF 271254885Sdumbbell#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 272254885Sdumbbell#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 273254885Sdumbbell#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 274254885Sdumbbell#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 275254885Sdumbbell#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 276254885Sdumbbell#define C_000040_DVI_I2C_INT 0xDFFFFFFF 277254885Sdumbbell#define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 278254885Sdumbbell#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 279254885Sdumbbell#define C_000040_GUIDMA 0xBFFFFFFF 280254885Sdumbbell#define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 281254885Sdumbbell#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 282254885Sdumbbell#define C_000040_VIDDMA 0x7FFFFFFF 283254885Sdumbbell#define R_000044_GEN_INT_STATUS 0x000044 284254885Sdumbbell#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 285254885Sdumbbell#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 286254885Sdumbbell#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 287254885Sdumbbell#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 288254885Sdumbbell#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 289254885Sdumbbell#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 290254885Sdumbbell#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 291254885Sdumbbell#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 292254885Sdumbbell#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 293254885Sdumbbell#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 294254885Sdumbbell#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 295254885Sdumbbell#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 296254885Sdumbbell#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 297254885Sdumbbell#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 298254885Sdumbbell#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 299254885Sdumbbell#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 300254885Sdumbbell#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 301254885Sdumbbell#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 302254885Sdumbbell#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 303254885Sdumbbell#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 304254885Sdumbbell#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 305254885Sdumbbell#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 306254885Sdumbbell#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 307254885Sdumbbell#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 308254885Sdumbbell#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 309254885Sdumbbell#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 310254885Sdumbbell#define C_000044_FP_DETECT_STAT 0xFFFFFFEF 311254885Sdumbbell#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 312254885Sdumbbell#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 313254885Sdumbbell#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 314254885Sdumbbell#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 315254885Sdumbbell#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 316254885Sdumbbell#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 317254885Sdumbbell#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 318254885Sdumbbell#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 319254885Sdumbbell#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 320254885Sdumbbell#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 321254885Sdumbbell#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 322254885Sdumbbell#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 323254885Sdumbbell#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 324254885Sdumbbell#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 325254885Sdumbbell#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 326254885Sdumbbell#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 327254885Sdumbbell#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 328254885Sdumbbell#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 329254885Sdumbbell#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 330254885Sdumbbell#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 331254885Sdumbbell#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 332254885Sdumbbell#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 333254885Sdumbbell#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 334254885Sdumbbell#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 335254885Sdumbbell#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 336254885Sdumbbell#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 337254885Sdumbbell#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 338254885Sdumbbell#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 339254885Sdumbbell#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 340254885Sdumbbell#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 341254885Sdumbbell#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 342254885Sdumbbell#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 343254885Sdumbbell#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 344254885Sdumbbell#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 345254885Sdumbbell#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 346254885Sdumbbell#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 347254885Sdumbbell#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 348254885Sdumbbell#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 349254885Sdumbbell#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 350254885Sdumbbell#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 351254885Sdumbbell#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 352254885Sdumbbell#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 353254885Sdumbbell#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 354254885Sdumbbell#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 355254885Sdumbbell#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 356254885Sdumbbell#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 357254885Sdumbbell#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 358254885Sdumbbell#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 359254885Sdumbbell#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 360254885Sdumbbell#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 361254885Sdumbbell#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 362254885Sdumbbell#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 363254885Sdumbbell#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 364254885Sdumbbell#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 365254885Sdumbbell#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 366254885Sdumbbell#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 367254885Sdumbbell#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 368254885Sdumbbell#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 369254885Sdumbbell#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 370254885Sdumbbell#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 371254885Sdumbbell#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 372254885Sdumbbell#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 373254885Sdumbbell#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 374254885Sdumbbell#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 375254885Sdumbbell#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 376254885Sdumbbell#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 377254885Sdumbbell#define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 378254885Sdumbbell#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 379254885Sdumbbell#define C_000044_I2C_INT 0xFFFDFFFF 380254885Sdumbbell#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 381254885Sdumbbell#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 382254885Sdumbbell#define C_000044_I2C_INT_AK 0xFFFDFFFF 383254885Sdumbbell#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 384254885Sdumbbell#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 385254885Sdumbbell#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 386254885Sdumbbell#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 387254885Sdumbbell#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 388254885Sdumbbell#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 389254885Sdumbbell#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 390254885Sdumbbell#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 391254885Sdumbbell#define C_000044_VIPH_INT 0xFEFFFFFF 392254885Sdumbbell#define S_000044_SW_INT(x) (((x) & 0x1) << 25) 393254885Sdumbbell#define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 394254885Sdumbbell#define C_000044_SW_INT 0xFDFFFFFF 395254885Sdumbbell#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 396254885Sdumbbell#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 397254885Sdumbbell#define C_000044_SW_INT_AK 0xFDFFFFFF 398254885Sdumbbell#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 399254885Sdumbbell#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 400254885Sdumbbell#define C_000044_SW_INT_SET 0xFBFFFFFF 401254885Sdumbbell#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 402254885Sdumbbell#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 403254885Sdumbbell#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 404254885Sdumbbell#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 405254885Sdumbbell#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 406254885Sdumbbell#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 407254885Sdumbbell#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 408254885Sdumbbell#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 409254885Sdumbbell#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 410254885Sdumbbell#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 411254885Sdumbbell#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 412254885Sdumbbell#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 413254885Sdumbbell#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 414254885Sdumbbell#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 415254885Sdumbbell#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 416254885Sdumbbell#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 417254885Sdumbbell#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 418254885Sdumbbell#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 419254885Sdumbbell#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 420254885Sdumbbell#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 421254885Sdumbbell#define C_000044_GUIDMA_STAT 0xBFFFFFFF 422254885Sdumbbell#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 423254885Sdumbbell#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 424254885Sdumbbell#define C_000044_GUIDMA_AK 0xBFFFFFFF 425254885Sdumbbell#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 426254885Sdumbbell#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 427254885Sdumbbell#define C_000044_VIDDMA_STAT 0x7FFFFFFF 428254885Sdumbbell#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 429254885Sdumbbell#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 430254885Sdumbbell#define C_000044_VIDDMA_AK 0x7FFFFFFF 431254885Sdumbbell#define R_000050_CRTC_GEN_CNTL 0x000050 432254885Sdumbbell#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 433254885Sdumbbell#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 434254885Sdumbbell#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 435254885Sdumbbell#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 436254885Sdumbbell#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 437254885Sdumbbell#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 438254885Sdumbbell#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 439254885Sdumbbell#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 440254885Sdumbbell#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 441254885Sdumbbell#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 442254885Sdumbbell#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 443254885Sdumbbell#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 444254885Sdumbbell#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 445254885Sdumbbell#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 446254885Sdumbbell#define C_000050_CRTC_ICON_EN 0xFFFF7FFF 447254885Sdumbbell#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 448254885Sdumbbell#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 449254885Sdumbbell#define C_000050_CRTC_CUR_EN 0xFFFEFFFF 450254885Sdumbbell#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 451254885Sdumbbell#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 452254885Sdumbbell#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 453254885Sdumbbell#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 454254885Sdumbbell#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 455254885Sdumbbell#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 456254885Sdumbbell#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 457254885Sdumbbell#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 458254885Sdumbbell#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 459254885Sdumbbell#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 460254885Sdumbbell#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 461254885Sdumbbell#define C_000050_CRTC_EN 0xFDFFFFFF 462254885Sdumbbell#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 463254885Sdumbbell#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 464254885Sdumbbell#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 465254885Sdumbbell#define R_000054_CRTC_EXT_CNTL 0x000054 466254885Sdumbbell#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 467254885Sdumbbell#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 468254885Sdumbbell#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 469254885Sdumbbell#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 470254885Sdumbbell#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 471254885Sdumbbell#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 472254885Sdumbbell#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 473254885Sdumbbell#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 474254885Sdumbbell#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 475254885Sdumbbell#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 476254885Sdumbbell#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 477254885Sdumbbell#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 478254885Sdumbbell#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 479254885Sdumbbell#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 480254885Sdumbbell#define C_000054_VGA_TEXT_132 0xFFFFFFDF 481254885Sdumbbell#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 482254885Sdumbbell#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 483254885Sdumbbell#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 484254885Sdumbbell#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 485254885Sdumbbell#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 486254885Sdumbbell#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 487254885Sdumbbell#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 488254885Sdumbbell#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 489254885Sdumbbell#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 490254885Sdumbbell#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 491254885Sdumbbell#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 492254885Sdumbbell#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 493254885Sdumbbell#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 494254885Sdumbbell#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 495254885Sdumbbell#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 496254885Sdumbbell#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 497254885Sdumbbell#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 498254885Sdumbbell#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 499254885Sdumbbell#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 500254885Sdumbbell#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 501254885Sdumbbell#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 502254885Sdumbbell#define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 503254885Sdumbbell#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 504254885Sdumbbell#define C_000054_CRT_ON 0xFFFF7FFF 505254885Sdumbbell#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 506254885Sdumbbell#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 507254885Sdumbbell#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 508254885Sdumbbell#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 509254885Sdumbbell#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 510254885Sdumbbell#define C_000054_VGA_PACK_DIS 0xFFFBFFFF 511254885Sdumbbell#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 512254885Sdumbbell#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 513254885Sdumbbell#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 514254885Sdumbbell#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 515254885Sdumbbell#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 516254885Sdumbbell#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 517254885Sdumbbell#define R_000148_MC_FB_LOCATION 0x000148 518254885Sdumbbell#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 519254885Sdumbbell#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 520254885Sdumbbell#define C_000148_MC_FB_START 0xFFFF0000 521254885Sdumbbell#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 522254885Sdumbbell#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 523254885Sdumbbell#define C_000148_MC_FB_TOP 0x0000FFFF 524254885Sdumbbell#define R_00014C_MC_AGP_LOCATION 0x00014C 525254885Sdumbbell#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 526254885Sdumbbell#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 527254885Sdumbbell#define C_00014C_MC_AGP_START 0xFFFF0000 528254885Sdumbbell#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 529254885Sdumbbell#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 530254885Sdumbbell#define C_00014C_MC_AGP_TOP 0x0000FFFF 531254885Sdumbbell#define R_000170_AGP_BASE 0x000170 532254885Sdumbbell#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 533254885Sdumbbell#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 534254885Sdumbbell#define C_000170_AGP_BASE_ADDR 0x00000000 535254885Sdumbbell#define R_00023C_DISPLAY_BASE_ADDR 0x00023C 536254885Sdumbbell#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 537254885Sdumbbell#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 538254885Sdumbbell#define C_00023C_DISPLAY_BASE_ADDR 0x00000000 539254885Sdumbbell#define R_000260_CUR_OFFSET 0x000260 540254885Sdumbbell#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 541254885Sdumbbell#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 542254885Sdumbbell#define C_000260_CUR_OFFSET 0xF8000000 543254885Sdumbbell#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 544254885Sdumbbell#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 545254885Sdumbbell#define C_000260_CUR_LOCK 0x7FFFFFFF 546254885Sdumbbell#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 547254885Sdumbbell#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 548254885Sdumbbell#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 549254885Sdumbbell#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 550254885Sdumbbell#define R_000360_CUR2_OFFSET 0x000360 551254885Sdumbbell#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 552254885Sdumbbell#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 553254885Sdumbbell#define C_000360_CUR2_OFFSET 0xF8000000 554254885Sdumbbell#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 555254885Sdumbbell#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 556254885Sdumbbell#define C_000360_CUR2_LOCK 0x7FFFFFFF 557254885Sdumbbell#define R_0003C2_GENMO_WT 0x0003C2 558254885Sdumbbell#define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 559254885Sdumbbell#define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 560254885Sdumbbell#define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 561254885Sdumbbell#define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 562254885Sdumbbell#define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 563254885Sdumbbell#define C_0003C2_VGA_RAM_EN 0xFD 564254885Sdumbbell#define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 565254885Sdumbbell#define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 566254885Sdumbbell#define C_0003C2_VGA_CKSEL 0xF3 567254885Sdumbbell#define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 568254885Sdumbbell#define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 569254885Sdumbbell#define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 570254885Sdumbbell#define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 571254885Sdumbbell#define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 572254885Sdumbbell#define C_0003C2_VGA_HSYNC_POL 0xBF 573254885Sdumbbell#define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 574254885Sdumbbell#define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 575254885Sdumbbell#define C_0003C2_VGA_VSYNC_POL 0x7F 576254885Sdumbbell#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 577254885Sdumbbell#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 578254885Sdumbbell#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 579254885Sdumbbell#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 580254885Sdumbbell#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 581254885Sdumbbell#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 582254885Sdumbbell#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 583254885Sdumbbell#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 584254885Sdumbbell#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 585254885Sdumbbell#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 586254885Sdumbbell#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 587254885Sdumbbell#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 588254885Sdumbbell#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 589254885Sdumbbell#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 590254885Sdumbbell#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 591254885Sdumbbell#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 592254885Sdumbbell#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 593254885Sdumbbell#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 594254885Sdumbbell#define C_0003F8_CRT2_ON 0xFFFFFF7F 595254885Sdumbbell#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 596254885Sdumbbell#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 597254885Sdumbbell#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 598254885Sdumbbell#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 599254885Sdumbbell#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 600254885Sdumbbell#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 601254885Sdumbbell#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 602254885Sdumbbell#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 603254885Sdumbbell#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 604254885Sdumbbell#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 605254885Sdumbbell#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 606254885Sdumbbell#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 607254885Sdumbbell#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 608254885Sdumbbell#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 609254885Sdumbbell#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 610254885Sdumbbell#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 611254885Sdumbbell#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 612254885Sdumbbell#define C_0003F8_CRTC2_EN 0xFDFFFFFF 613254885Sdumbbell#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 614254885Sdumbbell#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 615254885Sdumbbell#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 616254885Sdumbbell#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 617254885Sdumbbell#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 618254885Sdumbbell#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 619254885Sdumbbell#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 620254885Sdumbbell#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 621254885Sdumbbell#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 622254885Sdumbbell#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 623254885Sdumbbell#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 624254885Sdumbbell#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 625254885Sdumbbell#define R_000420_OV0_SCALE_CNTL 0x000420 626254885Sdumbbell#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 627254885Sdumbbell#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 628254885Sdumbbell#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 629254885Sdumbbell#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 630254885Sdumbbell#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 631254885Sdumbbell#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 632254885Sdumbbell#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 633254885Sdumbbell#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 634254885Sdumbbell#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 635254885Sdumbbell#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 636254885Sdumbbell#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 637254885Sdumbbell#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 638254885Sdumbbell#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 639254885Sdumbbell#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 640254885Sdumbbell#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 641254885Sdumbbell#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 642254885Sdumbbell#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 643254885Sdumbbell#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 644254885Sdumbbell#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 645254885Sdumbbell#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 646254885Sdumbbell#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 647254885Sdumbbell#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 648254885Sdumbbell#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 649254885Sdumbbell#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 650254885Sdumbbell#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 651254885Sdumbbell#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 652254885Sdumbbell#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 653254885Sdumbbell#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 654254885Sdumbbell#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 655254885Sdumbbell#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 656254885Sdumbbell#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 657254885Sdumbbell#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 658254885Sdumbbell#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 659254885Sdumbbell#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 660254885Sdumbbell#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 661254885Sdumbbell#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 662254885Sdumbbell#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 663254885Sdumbbell#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 664254885Sdumbbell#define C_000420_OV0_INT_EMU 0xDFFFFFFF 665254885Sdumbbell#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 666254885Sdumbbell#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 667254885Sdumbbell#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 668254885Sdumbbell#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 669254885Sdumbbell#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 670254885Sdumbbell#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 671254885Sdumbbell#define R_00070C_CP_RB_RPTR_ADDR 0x00070C 672254885Sdumbbell#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 673254885Sdumbbell#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 674254885Sdumbbell#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 675254885Sdumbbell#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 676254885Sdumbbell#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 677254885Sdumbbell#define C_00070C_RB_RPTR_ADDR 0x00000003 678254885Sdumbbell#define R_000740_CP_CSQ_CNTL 0x000740 679254885Sdumbbell#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 680254885Sdumbbell#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 681254885Sdumbbell#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 682254885Sdumbbell#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 683254885Sdumbbell#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 684254885Sdumbbell#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 685254885Sdumbbell#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 686254885Sdumbbell#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 687254885Sdumbbell#define C_000740_CSQ_MODE 0x0FFFFFFF 688254885Sdumbbell#define R_000770_SCRATCH_UMSK 0x000770 689254885Sdumbbell#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 690254885Sdumbbell#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 691254885Sdumbbell#define C_000770_SCRATCH_UMSK 0xFFFFFFC0 692254885Sdumbbell#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 693254885Sdumbbell#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 694254885Sdumbbell#define C_000770_SCRATCH_SWAP 0xFFFCFFFF 695254885Sdumbbell#define R_000774_SCRATCH_ADDR 0x000774 696254885Sdumbbell#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 697254885Sdumbbell#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 698254885Sdumbbell#define C_000774_SCRATCH_ADDR 0x0000001F 699254885Sdumbbell#define R_0007C0_CP_STAT 0x0007C0 700254885Sdumbbell#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 701254885Sdumbbell#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 702254885Sdumbbell#define C_0007C0_MRU_BUSY 0xFFFFFFFE 703254885Sdumbbell#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 704254885Sdumbbell#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 705254885Sdumbbell#define C_0007C0_MWU_BUSY 0xFFFFFFFD 706254885Sdumbbell#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 707254885Sdumbbell#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 708254885Sdumbbell#define C_0007C0_RSIU_BUSY 0xFFFFFFFB 709254885Sdumbbell#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 710254885Sdumbbell#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 711254885Sdumbbell#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 712254885Sdumbbell#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 713254885Sdumbbell#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 714254885Sdumbbell#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 715254885Sdumbbell#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 716254885Sdumbbell#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 717254885Sdumbbell#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 718254885Sdumbbell#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 719254885Sdumbbell#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 720254885Sdumbbell#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 721254885Sdumbbell#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 722254885Sdumbbell#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 723254885Sdumbbell#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 724254885Sdumbbell#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 725254885Sdumbbell#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 726254885Sdumbbell#define C_0007C0_CSI_BUSY 0xFFFFDFFF 727254885Sdumbbell#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 728254885Sdumbbell#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 729254885Sdumbbell#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 730254885Sdumbbell#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 731254885Sdumbbell#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 732254885Sdumbbell#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 733254885Sdumbbell#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 734254885Sdumbbell#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 735254885Sdumbbell#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 736254885Sdumbbell#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 737254885Sdumbbell#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 738254885Sdumbbell#define C_0007C0_CP_BUSY 0x7FFFFFFF 739254885Sdumbbell#define R_000E40_RBBM_STATUS 0x000E40 740254885Sdumbbell#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 741254885Sdumbbell#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 742254885Sdumbbell#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 743254885Sdumbbell#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 744254885Sdumbbell#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 745254885Sdumbbell#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 746254885Sdumbbell#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 747254885Sdumbbell#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 748254885Sdumbbell#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 749254885Sdumbbell#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 750254885Sdumbbell#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 751254885Sdumbbell#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 752254885Sdumbbell#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 753254885Sdumbbell#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 754254885Sdumbbell#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 755254885Sdumbbell#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 756254885Sdumbbell#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 757254885Sdumbbell#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 758254885Sdumbbell#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 759254885Sdumbbell#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 760254885Sdumbbell#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 761254885Sdumbbell#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 762254885Sdumbbell#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 763254885Sdumbbell#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 764254885Sdumbbell#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 765254885Sdumbbell#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 766254885Sdumbbell#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 767254885Sdumbbell#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 768254885Sdumbbell#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 769254885Sdumbbell#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 770254885Sdumbbell#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 771254885Sdumbbell#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 772254885Sdumbbell#define C_000E40_E2_BUSY 0xFFFDFFFF 773254885Sdumbbell#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 774254885Sdumbbell#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 775254885Sdumbbell#define C_000E40_RB2D_BUSY 0xFFFBFFFF 776254885Sdumbbell#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 777254885Sdumbbell#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 778254885Sdumbbell#define C_000E40_RB3D_BUSY 0xFFF7FFFF 779254885Sdumbbell#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 780254885Sdumbbell#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 781254885Sdumbbell#define C_000E40_SE_BUSY 0xFFEFFFFF 782254885Sdumbbell#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 783254885Sdumbbell#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 784254885Sdumbbell#define C_000E40_RE_BUSY 0xFFDFFFFF 785254885Sdumbbell#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 786254885Sdumbbell#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 787254885Sdumbbell#define C_000E40_TAM_BUSY 0xFFBFFFFF 788254885Sdumbbell#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 789254885Sdumbbell#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 790254885Sdumbbell#define C_000E40_TDM_BUSY 0xFF7FFFFF 791254885Sdumbbell#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 792254885Sdumbbell#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 793254885Sdumbbell#define C_000E40_PB_BUSY 0xFEFFFFFF 794254885Sdumbbell#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 795254885Sdumbbell#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 796254885Sdumbbell#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 797254885Sdumbbell 798254885Sdumbbell 799254885Sdumbbell#define R_00000D_SCLK_CNTL 0x00000D 800254885Sdumbbell#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 801254885Sdumbbell#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 802254885Sdumbbell#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 803254885Sdumbbell#define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 804254885Sdumbbell#define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 805254885Sdumbbell#define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 806254885Sdumbbell#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 807254885Sdumbbell#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 808254885Sdumbbell#define C_00000D_FORCE_CP 0xFFFEFFFF 809254885Sdumbbell#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 810254885Sdumbbell#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 811254885Sdumbbell#define C_00000D_FORCE_HDP 0xFFFDFFFF 812254885Sdumbbell#define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 813254885Sdumbbell#define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 814254885Sdumbbell#define C_00000D_FORCE_DISP 0xFFFBFFFF 815254885Sdumbbell#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 816254885Sdumbbell#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 817254885Sdumbbell#define C_00000D_FORCE_TOP 0xFFF7FFFF 818254885Sdumbbell#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 819254885Sdumbbell#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 820254885Sdumbbell#define C_00000D_FORCE_E2 0xFFEFFFFF 821254885Sdumbbell#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 822254885Sdumbbell#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 823254885Sdumbbell#define C_00000D_FORCE_SE 0xFFDFFFFF 824254885Sdumbbell#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 825254885Sdumbbell#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 826254885Sdumbbell#define C_00000D_FORCE_IDCT 0xFFBFFFFF 827254885Sdumbbell#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 828254885Sdumbbell#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 829254885Sdumbbell#define C_00000D_FORCE_VIP 0xFF7FFFFF 830254885Sdumbbell#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 831254885Sdumbbell#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 832254885Sdumbbell#define C_00000D_FORCE_RE 0xFEFFFFFF 833254885Sdumbbell#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 834254885Sdumbbell#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 835254885Sdumbbell#define C_00000D_FORCE_PB 0xFDFFFFFF 836254885Sdumbbell#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 837254885Sdumbbell#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 838254885Sdumbbell#define C_00000D_FORCE_TAM 0xFBFFFFFF 839254885Sdumbbell#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 840254885Sdumbbell#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 841254885Sdumbbell#define C_00000D_FORCE_TDM 0xF7FFFFFF 842254885Sdumbbell#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 843254885Sdumbbell#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 844254885Sdumbbell#define C_00000D_FORCE_RB 0xEFFFFFFF 845254885Sdumbbell 846254885Sdumbbell/* PLL regs */ 847254885Sdumbbell#define SCLK_CNTL 0xd 848254885Sdumbbell#define FORCE_HDP (1 << 17) 849254885Sdumbbell#define CLK_PWRMGT_CNTL 0x14 850254885Sdumbbell#define GLOBAL_PMAN_EN (1 << 10) 851254885Sdumbbell#define DISP_PM (1 << 20) 852254885Sdumbbell#define PLL_PWRMGT_CNTL 0x15 853254885Sdumbbell#define MPLL_TURNOFF (1 << 0) 854254885Sdumbbell#define SPLL_TURNOFF (1 << 1) 855254885Sdumbbell#define PPLL_TURNOFF (1 << 2) 856254885Sdumbbell#define P2PLL_TURNOFF (1 << 3) 857254885Sdumbbell#define TVPLL_TURNOFF (1 << 4) 858254885Sdumbbell#define MOBILE_SU (1 << 16) 859254885Sdumbbell#define SU_SCLK_USE_BCLK (1 << 17) 860254885Sdumbbell#define SCLK_CNTL2 0x1e 861254885Sdumbbell#define REDUCED_SPEED_SCLK_MODE (1 << 16) 862254885Sdumbbell#define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 863254885Sdumbbell#define MCLK_MISC 0x1f 864254885Sdumbbell#define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 865254885Sdumbbell#define SCLK_MORE_CNTL 0x35 866254885Sdumbbell#define REDUCED_SPEED_SCLK_EN (1 << 16) 867254885Sdumbbell#define IO_CG_VOLTAGE_DROP (1 << 17) 868254885Sdumbbell#define VOLTAGE_DELAY_SEL(x) ((x) << 20) 869254885Sdumbbell#define VOLTAGE_DROP_SYNC (1 << 19) 870254885Sdumbbell 871254885Sdumbbell/* mmreg */ 872254885Sdumbbell#define DISP_PWR_MAN 0xd08 873254885Sdumbbell#define DISP_D3_GRPH_RST (1 << 18) 874254885Sdumbbell#define DISP_D3_SUBPIC_RST (1 << 19) 875254885Sdumbbell#define DISP_D3_OV0_RST (1 << 20) 876254885Sdumbbell#define DISP_D1D2_GRPH_RST (1 << 21) 877254885Sdumbbell#define DISP_D1D2_SUBPIC_RST (1 << 22) 878254885Sdumbbell#define DISP_D1D2_OV0_RST (1 << 23) 879254885Sdumbbell#define DISP_DVO_ENABLE_RST (1 << 24) 880254885Sdumbbell#define TV_ENABLE_RST (1 << 25) 881254885Sdumbbell#define AUTO_PWRUP_EN (1 << 26) 882254885Sdumbbell 883254885Sdumbbell#endif 884