1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/11/sys/dev/qlnx/qlnxe/ecore_hsi_roce.h 337517 2018-08-09 01:17:35Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs#ifndef __ECORE_HSI_ROCE__ 32316485Sdavidcs#define __ECORE_HSI_ROCE__ 33316485Sdavidcs/************************************************************************/ 34316485Sdavidcs/* Add include to ecore hsi rdma target for both roce and iwarp ecore driver */ 35316485Sdavidcs/************************************************************************/ 36316485Sdavidcs#include "ecore_hsi_rdma.h" 37316485Sdavidcs/************************************************************************/ 38316485Sdavidcs/* Add include to common roce target for both eCore and protocol roce driver */ 39316485Sdavidcs/************************************************************************/ 40316485Sdavidcs#include "roce_common.h" 41316485Sdavidcs 42316485Sdavidcs/* 43320164Sdavidcs * The roce storm context of Ystorm 44316485Sdavidcs */ 45320164Sdavidcsstruct ystorm_roce_conn_st_ctx 46316485Sdavidcs{ 47320164Sdavidcs struct regpair temp[2]; 48316485Sdavidcs}; 49316485Sdavidcs 50316485Sdavidcs/* 51316485Sdavidcs * The roce storm context of Mstorm 52316485Sdavidcs */ 53316485Sdavidcsstruct pstorm_roce_conn_st_ctx 54316485Sdavidcs{ 55316485Sdavidcs struct regpair temp[16]; 56316485Sdavidcs}; 57316485Sdavidcs 58316485Sdavidcs/* 59316485Sdavidcs * The roce storm context of Xstorm 60316485Sdavidcs */ 61316485Sdavidcsstruct xstorm_roce_conn_st_ctx 62316485Sdavidcs{ 63316485Sdavidcs struct regpair temp[24]; 64316485Sdavidcs}; 65316485Sdavidcs 66316485Sdavidcs/* 67316485Sdavidcs * The roce storm context of Tstorm 68316485Sdavidcs */ 69316485Sdavidcsstruct tstorm_roce_conn_st_ctx 70316485Sdavidcs{ 71316485Sdavidcs struct regpair temp[30]; 72316485Sdavidcs}; 73316485Sdavidcs 74316485Sdavidcs/* 75320164Sdavidcs * The roce storm context of Mstorm 76320164Sdavidcs */ 77320164Sdavidcsstruct mstorm_roce_conn_st_ctx 78320164Sdavidcs{ 79320164Sdavidcs struct regpair temp[6]; 80320164Sdavidcs}; 81320164Sdavidcs 82320164Sdavidcs/* 83316485Sdavidcs * The roce storm context of Ystorm 84316485Sdavidcs */ 85316485Sdavidcsstruct ustorm_roce_conn_st_ctx 86316485Sdavidcs{ 87316485Sdavidcs struct regpair temp[12]; 88316485Sdavidcs}; 89316485Sdavidcs 90316485Sdavidcs/* 91316485Sdavidcs * roce connection context 92316485Sdavidcs */ 93320164Sdavidcsstruct e4_roce_conn_context 94316485Sdavidcs{ 95316485Sdavidcs struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 96316485Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 97316485Sdavidcs struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 98316485Sdavidcs struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 99316485Sdavidcs struct regpair xstorm_st_padding[2] /* padding */; 100316485Sdavidcs struct e4_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 101316485Sdavidcs struct e4_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 102316485Sdavidcs struct timers_context timer_context /* timer context */; 103316485Sdavidcs struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 104316485Sdavidcs struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 105316485Sdavidcs struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 106316485Sdavidcs struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 107316485Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 108316485Sdavidcs}; 109316485Sdavidcs 110316485Sdavidcs 111316485Sdavidcs/* 112320164Sdavidcs * roce connection context 113320164Sdavidcs */ 114320164Sdavidcsstruct e5_roce_conn_context 115320164Sdavidcs{ 116320164Sdavidcs struct ystorm_roce_conn_st_ctx ystorm_st_context /* ystorm storm context */; 117320164Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 118320164Sdavidcs struct pstorm_roce_conn_st_ctx pstorm_st_context /* pstorm storm context */; 119320164Sdavidcs struct xstorm_roce_conn_st_ctx xstorm_st_context /* xstorm storm context */; 120320164Sdavidcs struct regpair xstorm_st_padding[2] /* padding */; 121320164Sdavidcs struct e5_xstorm_rdma_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 122320164Sdavidcs struct e5_tstorm_rdma_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 123320164Sdavidcs struct timers_context timer_context /* timer context */; 124320164Sdavidcs struct e5_ustorm_rdma_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 125320164Sdavidcs struct tstorm_roce_conn_st_ctx tstorm_st_context /* tstorm storm context */; 126320164Sdavidcs struct mstorm_roce_conn_st_ctx mstorm_st_context /* mstorm storm context */; 127320164Sdavidcs struct ustorm_roce_conn_st_ctx ustorm_st_context /* ustorm storm context */; 128320164Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 129320164Sdavidcs}; 130320164Sdavidcs 131320164Sdavidcs 132320164Sdavidcs 133320164Sdavidcs 134320164Sdavidcs/* 135316485Sdavidcs * roce create qp requester ramrod data 136316485Sdavidcs */ 137316485Sdavidcsstruct roce_create_qp_req_ramrod_data 138316485Sdavidcs{ 139316485Sdavidcs __le16 flags; 140316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 141316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 142316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 143316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 144316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 145316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 146316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 147316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 148337517Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 149337517Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 150316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 151316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 152316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 153316485Sdavidcs#define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 154316485Sdavidcs u8 max_ord; 155316485Sdavidcs u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 156316485Sdavidcs u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 157316485Sdavidcs u8 orq_num_pages; 158316485Sdavidcs __le16 p_key; 159316485Sdavidcs __le32 flow_label; 160316485Sdavidcs __le32 dst_qp_id; 161316485Sdavidcs __le32 ack_timeout_val; 162316485Sdavidcs __le32 initial_psn; 163316485Sdavidcs __le16 mtu; 164316485Sdavidcs __le16 pd; 165316485Sdavidcs __le16 sq_num_pages; 166316485Sdavidcs __le16 low_latency_phy_queue; 167316485Sdavidcs struct regpair sq_pbl_addr; 168316485Sdavidcs struct regpair orq_pbl_addr; 169316485Sdavidcs __le16 local_mac_addr[3] /* BE order */; 170316485Sdavidcs __le16 remote_mac_addr[3] /* BE order */; 171316485Sdavidcs __le16 vlan_id; 172316485Sdavidcs __le16 udp_src_port /* Only relevant in RRoCE */; 173316485Sdavidcs __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 174316485Sdavidcs __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the high register will hold the address. Low registers must be zero! */; 175337517Sdavidcs __le32 cq_cid; 176316485Sdavidcs struct regpair qp_handle_for_cqe; 177316485Sdavidcs struct regpair qp_handle_for_async; 178316485Sdavidcs u8 stats_counter_id /* Statistics counter ID to use */; 179316485Sdavidcs u8 reserved3[7]; 180316485Sdavidcs __le16 regular_latency_phy_queue; 181316485Sdavidcs __le16 dpi; 182316485Sdavidcs}; 183316485Sdavidcs 184316485Sdavidcs 185316485Sdavidcs/* 186316485Sdavidcs * roce create qp responder ramrod data 187316485Sdavidcs */ 188316485Sdavidcsstruct roce_create_qp_resp_ramrod_data 189316485Sdavidcs{ 190337517Sdavidcs __le32 flags; 191316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 192316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 193316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 194316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 195316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 196316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 197316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 198316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 199316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 200316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 201316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 202316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 203316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 204316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 205316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 206316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 207316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 208316485Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 209337517Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 210337517Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 211337517Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x7FFF 212337517Sdavidcs#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 17 213337517Sdavidcs __le16 xrc_domain /* SRC domain. Only applicable when xrc_flag is set */; 214316485Sdavidcs u8 max_ird; 215316485Sdavidcs u8 traffic_class /* In case of RRoCE on IPv4 will be used as TOS */; 216316485Sdavidcs u8 hop_limit /* In case of RRoCE on IPv4 will be used as TTL */; 217316485Sdavidcs u8 irq_num_pages; 218316485Sdavidcs __le16 p_key; 219316485Sdavidcs __le32 flow_label; 220316485Sdavidcs __le32 dst_qp_id; 221316485Sdavidcs u8 stats_counter_id /* Statistics counter ID to use */; 222316485Sdavidcs u8 reserved1; 223316485Sdavidcs __le16 mtu; 224316485Sdavidcs __le32 initial_psn; 225316485Sdavidcs __le16 pd; 226316485Sdavidcs __le16 rq_num_pages; 227316485Sdavidcs struct rdma_srq_id srq_id; 228316485Sdavidcs struct regpair rq_pbl_addr; 229316485Sdavidcs struct regpair irq_pbl_addr; 230316485Sdavidcs __le16 local_mac_addr[3] /* BE order */; 231316485Sdavidcs __le16 remote_mac_addr[3] /* BE order */; 232316485Sdavidcs __le16 vlan_id; 233316485Sdavidcs __le16 udp_src_port /* Only relevant in RRoCE */; 234316485Sdavidcs __le32 src_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 235316485Sdavidcs __le32 dst_gid[4] /* BE order. In case of RRoCE on IPv4 the lower register will hold the address. High registers must be zero! */; 236316485Sdavidcs struct regpair qp_handle_for_cqe; 237316485Sdavidcs struct regpair qp_handle_for_async; 238316485Sdavidcs __le16 low_latency_phy_queue; 239337517Sdavidcs u8 reserved2[2]; 240316485Sdavidcs __le32 cq_cid; 241316485Sdavidcs __le16 regular_latency_phy_queue; 242316485Sdavidcs __le16 dpi; 243316485Sdavidcs}; 244316485Sdavidcs 245316485Sdavidcs 246316485Sdavidcs/* 247337517Sdavidcs * roce DCQCN received statistics 248337517Sdavidcs */ 249337517Sdavidcsstruct roce_dcqcn_received_stats 250337517Sdavidcs{ 251337517Sdavidcs struct regpair ecn_pkt_rcv /* The number of total packets with ECN indication received */; 252337517Sdavidcs struct regpair cnp_pkt_rcv /* The number of total RoCE packets with CNP opcode received */; 253337517Sdavidcs}; 254337517Sdavidcs 255337517Sdavidcs 256337517Sdavidcs/* 257337517Sdavidcs * roce DCQCN sent statistics 258337517Sdavidcs */ 259337517Sdavidcsstruct roce_dcqcn_sent_stats 260337517Sdavidcs{ 261337517Sdavidcs struct regpair cnp_pkt_sent /* The number of total RoCE packets with CNP opcode sent */; 262337517Sdavidcs}; 263337517Sdavidcs 264337517Sdavidcs 265337517Sdavidcs/* 266316485Sdavidcs * RoCE destroy qp requester output params 267316485Sdavidcs */ 268316485Sdavidcsstruct roce_destroy_qp_req_output_params 269316485Sdavidcs{ 270316485Sdavidcs __le32 num_bound_mw; 271316485Sdavidcs __le32 cq_prod /* Completion producer value at destroy QP */; 272316485Sdavidcs}; 273316485Sdavidcs 274316485Sdavidcs 275316485Sdavidcs/* 276316485Sdavidcs * RoCE destroy qp requester ramrod data 277316485Sdavidcs */ 278316485Sdavidcsstruct roce_destroy_qp_req_ramrod_data 279316485Sdavidcs{ 280316485Sdavidcs struct regpair output_params_addr; 281316485Sdavidcs}; 282316485Sdavidcs 283316485Sdavidcs 284316485Sdavidcs/* 285316485Sdavidcs * RoCE destroy qp responder output params 286316485Sdavidcs */ 287316485Sdavidcsstruct roce_destroy_qp_resp_output_params 288316485Sdavidcs{ 289316485Sdavidcs __le32 num_invalidated_mw; 290316485Sdavidcs __le32 cq_prod /* Completion producer value at destroy QP */; 291316485Sdavidcs}; 292316485Sdavidcs 293316485Sdavidcs 294316485Sdavidcs/* 295316485Sdavidcs * RoCE destroy qp responder ramrod data 296316485Sdavidcs */ 297316485Sdavidcsstruct roce_destroy_qp_resp_ramrod_data 298316485Sdavidcs{ 299316485Sdavidcs struct regpair output_params_addr; 300316485Sdavidcs}; 301316485Sdavidcs 302316485Sdavidcs 303316485Sdavidcs/* 304337517Sdavidcs * roce special events statistics 305316485Sdavidcs */ 306316485Sdavidcsstruct roce_events_stats 307316485Sdavidcs{ 308316485Sdavidcs __le16 silent_drops; 309316485Sdavidcs __le16 rnr_naks_sent; 310316485Sdavidcs __le32 retransmit_count; 311316485Sdavidcs __le32 icrc_error_count; 312316485Sdavidcs __le32 reserved; 313316485Sdavidcs}; 314316485Sdavidcs 315316485Sdavidcs 316316485Sdavidcs/* 317316485Sdavidcs * ROCE slow path EQ cmd IDs 318316485Sdavidcs */ 319316485Sdavidcsenum roce_event_opcode 320316485Sdavidcs{ 321316485Sdavidcs ROCE_EVENT_CREATE_QP=11, 322316485Sdavidcs ROCE_EVENT_MODIFY_QP, 323316485Sdavidcs ROCE_EVENT_QUERY_QP, 324316485Sdavidcs ROCE_EVENT_DESTROY_QP, 325316485Sdavidcs ROCE_EVENT_CREATE_UD_QP, 326316485Sdavidcs ROCE_EVENT_DESTROY_UD_QP, 327316485Sdavidcs MAX_ROCE_EVENT_OPCODE 328316485Sdavidcs}; 329316485Sdavidcs 330316485Sdavidcs 331316485Sdavidcs/* 332316485Sdavidcs * roce func init ramrod data 333316485Sdavidcs */ 334316485Sdavidcsstruct roce_init_func_params 335316485Sdavidcs{ 336316485Sdavidcs u8 ll2_queue_id /* This ll2 queue ID is used for Unreliable Datagram QP */; 337316485Sdavidcs u8 cnp_vlan_priority /* VLAN priority of DCQCN CNP packet */; 338316485Sdavidcs u8 cnp_dscp /* The value of DSCP field in IP header for CNP packets */; 339316485Sdavidcs u8 reserved; 340316485Sdavidcs __le32 cnp_send_timeout /* The minimal difference of send time between CNP packets for specific QP. Units are in microseconds */; 341316485Sdavidcs}; 342316485Sdavidcs 343316485Sdavidcs 344316485Sdavidcs/* 345316485Sdavidcs * roce func init ramrod data 346316485Sdavidcs */ 347316485Sdavidcsstruct roce_init_func_ramrod_data 348316485Sdavidcs{ 349316485Sdavidcs struct rdma_init_func_ramrod_data rdma; 350316485Sdavidcs struct roce_init_func_params roce; 351316485Sdavidcs}; 352316485Sdavidcs 353316485Sdavidcs 354316485Sdavidcs/* 355316485Sdavidcs * roce modify qp requester ramrod data 356316485Sdavidcs */ 357316485Sdavidcsstruct roce_modify_qp_req_ramrod_data 358316485Sdavidcs{ 359316485Sdavidcs __le16 flags; 360316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 361316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 362316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 363316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 364316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 365316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 366316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 367316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 368316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 369316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 370316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 371316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 372316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 373316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 374316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 375316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 376316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 377316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 378316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 379316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 380316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 381316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 382337517Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 383337517Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 13 384337517Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 385337517Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 386316485Sdavidcs u8 fields; 387316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 388316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 389316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 390316485Sdavidcs#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 391316485Sdavidcs u8 max_ord; 392316485Sdavidcs u8 traffic_class; 393316485Sdavidcs u8 hop_limit; 394316485Sdavidcs __le16 p_key; 395316485Sdavidcs __le32 flow_label; 396316485Sdavidcs __le32 ack_timeout_val; 397316485Sdavidcs __le16 mtu; 398316485Sdavidcs __le16 reserved2; 399337517Sdavidcs __le32 reserved3[2]; 400337517Sdavidcs __le16 low_latency_phy_queue; 401337517Sdavidcs __le16 regular_latency_phy_queue; 402316485Sdavidcs __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 403316485Sdavidcs __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 404316485Sdavidcs}; 405316485Sdavidcs 406316485Sdavidcs 407316485Sdavidcs/* 408316485Sdavidcs * roce modify qp responder ramrod data 409316485Sdavidcs */ 410316485Sdavidcsstruct roce_modify_qp_resp_ramrod_data 411316485Sdavidcs{ 412316485Sdavidcs __le16 flags; 413316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 414316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 415316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 416316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 417316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 418316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 419316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 420316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 421316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 422316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 423316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 424316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 425316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 426316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 427316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 428316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 429316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 430316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 431316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 432316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 433337517Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK 0x1 434337517Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT 10 435337517Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 436337517Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 437316485Sdavidcs u8 fields; 438316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 439316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 440316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 441316485Sdavidcs#define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 442316485Sdavidcs u8 max_ird; 443316485Sdavidcs u8 traffic_class; 444316485Sdavidcs u8 hop_limit; 445316485Sdavidcs __le16 p_key; 446316485Sdavidcs __le32 flow_label; 447316485Sdavidcs __le16 mtu; 448337517Sdavidcs __le16 low_latency_phy_queue; 449337517Sdavidcs __le16 regular_latency_phy_queue; 450337517Sdavidcs u8 reserved2[6]; 451316485Sdavidcs __le32 src_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 452316485Sdavidcs __le32 dst_gid[4] /* BE order. In case of IPv4 the higher register will hold the address. Low registers must be zero! */; 453316485Sdavidcs}; 454316485Sdavidcs 455316485Sdavidcs 456316485Sdavidcs/* 457316485Sdavidcs * RoCE query qp requester output params 458316485Sdavidcs */ 459316485Sdavidcsstruct roce_query_qp_req_output_params 460316485Sdavidcs{ 461316485Sdavidcs __le32 psn /* send next psn */; 462316485Sdavidcs __le32 flags; 463316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 464316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 465316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 466316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 467316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 468316485Sdavidcs#define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 469316485Sdavidcs}; 470316485Sdavidcs 471316485Sdavidcs 472316485Sdavidcs/* 473316485Sdavidcs * RoCE query qp requester ramrod data 474316485Sdavidcs */ 475316485Sdavidcsstruct roce_query_qp_req_ramrod_data 476316485Sdavidcs{ 477316485Sdavidcs struct regpair output_params_addr; 478316485Sdavidcs}; 479316485Sdavidcs 480316485Sdavidcs 481316485Sdavidcs/* 482316485Sdavidcs * RoCE query qp responder output params 483316485Sdavidcs */ 484316485Sdavidcsstruct roce_query_qp_resp_output_params 485316485Sdavidcs{ 486316485Sdavidcs __le32 psn /* send next psn */; 487316485Sdavidcs __le32 err_flag; 488316485Sdavidcs#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 489316485Sdavidcs#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 490316485Sdavidcs#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 491316485Sdavidcs#define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 492316485Sdavidcs}; 493316485Sdavidcs 494316485Sdavidcs 495316485Sdavidcs/* 496316485Sdavidcs * RoCE query qp responder ramrod data 497316485Sdavidcs */ 498316485Sdavidcsstruct roce_query_qp_resp_ramrod_data 499316485Sdavidcs{ 500316485Sdavidcs struct regpair output_params_addr; 501316485Sdavidcs}; 502316485Sdavidcs 503316485Sdavidcs 504316485Sdavidcs/* 505316485Sdavidcs * ROCE ramrod command IDs 506316485Sdavidcs */ 507316485Sdavidcsenum roce_ramrod_cmd_id 508316485Sdavidcs{ 509316485Sdavidcs ROCE_RAMROD_CREATE_QP=11, 510316485Sdavidcs ROCE_RAMROD_MODIFY_QP, 511316485Sdavidcs ROCE_RAMROD_QUERY_QP, 512316485Sdavidcs ROCE_RAMROD_DESTROY_QP, 513316485Sdavidcs ROCE_RAMROD_CREATE_UD_QP, 514316485Sdavidcs ROCE_RAMROD_DESTROY_UD_QP, 515316485Sdavidcs MAX_ROCE_RAMROD_CMD_ID 516316485Sdavidcs}; 517316485Sdavidcs 518316485Sdavidcs 519316485Sdavidcs 520316485Sdavidcs 521316485Sdavidcs 522316485Sdavidcs 523316485Sdavidcsstruct e4_mstorm_roce_req_conn_ag_ctx 524316485Sdavidcs{ 525316485Sdavidcs u8 byte0 /* cdu_validation */; 526316485Sdavidcs u8 byte1 /* state */; 527316485Sdavidcs u8 flags0; 528316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 529316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 530316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 531316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 532316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 533316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 534316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 535316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 536316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 537316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 538316485Sdavidcs u8 flags1; 539316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 540316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 541316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 542316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 543316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 544316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 545316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 546316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 547316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 548316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 549316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 550316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 551316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 552316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 553316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 554316485Sdavidcs#define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 555316485Sdavidcs __le16 word0 /* word0 */; 556316485Sdavidcs __le16 word1 /* word1 */; 557316485Sdavidcs __le32 reg0 /* reg0 */; 558316485Sdavidcs __le32 reg1 /* reg1 */; 559316485Sdavidcs}; 560316485Sdavidcs 561316485Sdavidcs 562316485Sdavidcsstruct e4_mstorm_roce_resp_conn_ag_ctx 563316485Sdavidcs{ 564316485Sdavidcs u8 byte0 /* cdu_validation */; 565316485Sdavidcs u8 byte1 /* state */; 566316485Sdavidcs u8 flags0; 567316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 568316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 569316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 570316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 571316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 572316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 573316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 574316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 575316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 576316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 577316485Sdavidcs u8 flags1; 578316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 579316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 580316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 581316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 582316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 583316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 584316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 585316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 586316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 587316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 588316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 589316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 590316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 591316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 592316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 593316485Sdavidcs#define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 594316485Sdavidcs __le16 word0 /* word0 */; 595316485Sdavidcs __le16 word1 /* word1 */; 596316485Sdavidcs __le32 reg0 /* reg0 */; 597316485Sdavidcs __le32 reg1 /* reg1 */; 598316485Sdavidcs}; 599316485Sdavidcs 600316485Sdavidcs 601316485Sdavidcsstruct e4_tstorm_roce_req_conn_ag_ctx 602316485Sdavidcs{ 603316485Sdavidcs u8 reserved0 /* cdu_validation */; 604316485Sdavidcs u8 state /* state */; 605316485Sdavidcs u8 flags0; 606316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 607316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 608316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 609316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 610316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 611316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 612316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 613316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 614316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 615316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 616316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 617316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 618316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 619316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 620316485Sdavidcs u8 flags1; 621316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 622316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 623316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 624316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 625316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 626316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 627316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 628316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 629316485Sdavidcs u8 flags2; 630316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 631316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 632316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 633316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 634316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 635316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 636316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 637316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 638316485Sdavidcs u8 flags3; 639316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 640316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 641316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 642316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 643316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 644316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 645316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 646316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 647316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 648316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 649316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 650316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 651316485Sdavidcs u8 flags4; 652316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 653316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 654316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 655316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 656316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 657316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 658316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 659316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 660316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 661316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 662316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 663316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 664316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 665316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 666316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 667316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 668316485Sdavidcs u8 flags5; 669316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 670316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 671316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 672316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 673316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 674316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 675316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 676316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 677316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 678316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 679316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 680316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 681316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 682316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 683316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 684316485Sdavidcs#define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 685316485Sdavidcs __le32 reg0 /* reg0 */; 686316485Sdavidcs __le32 snd_nxt_psn /* reg1 */; 687316485Sdavidcs __le32 snd_max_psn /* reg2 */; 688316485Sdavidcs __le32 orq_prod /* reg3 */; 689316485Sdavidcs __le32 reg4 /* reg4 */; 690316485Sdavidcs __le32 reg5 /* reg5 */; 691316485Sdavidcs __le32 reg6 /* reg6 */; 692316485Sdavidcs __le32 reg7 /* reg7 */; 693316485Sdavidcs __le32 reg8 /* reg8 */; 694316485Sdavidcs u8 tx_cqe_error_type /* byte2 */; 695316485Sdavidcs u8 orq_cache_idx /* byte3 */; 696316485Sdavidcs __le16 snd_sq_cons_th /* word0 */; 697316485Sdavidcs u8 byte4 /* byte4 */; 698316485Sdavidcs u8 byte5 /* byte5 */; 699316485Sdavidcs __le16 snd_sq_cons /* word1 */; 700337517Sdavidcs __le16 conn_dpi /* conn_dpi */; 701316485Sdavidcs __le16 word3 /* word3 */; 702316485Sdavidcs __le32 reg9 /* reg9 */; 703316485Sdavidcs __le32 reg10 /* reg10 */; 704316485Sdavidcs}; 705316485Sdavidcs 706316485Sdavidcs 707316485Sdavidcsstruct e4_tstorm_roce_resp_conn_ag_ctx 708316485Sdavidcs{ 709316485Sdavidcs u8 byte0 /* cdu_validation */; 710316485Sdavidcs u8 state /* state */; 711316485Sdavidcs u8 flags0; 712316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 713316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 714316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 715316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 716316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 717316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 718316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 719316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 720316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 721316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 722316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 723316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 724316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 725316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 726316485Sdavidcs u8 flags1; 727316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 728316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 729316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 730316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 731316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 732316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 733316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 734316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 735316485Sdavidcs u8 flags2; 736316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 737316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 738316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 739316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 740316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 741316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 742316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 743316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 744316485Sdavidcs u8 flags3; 745316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 746316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 747316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 748316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 749316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 750316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 751316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 752316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 753316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 754316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 755316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 756316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 757316485Sdavidcs u8 flags4; 758316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 759316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 760316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 761316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 762316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 763316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 764316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 765316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 766316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 767316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 768316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 769316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 770316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 771316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 772316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 773316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 774316485Sdavidcs u8 flags5; 775316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 776316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 777316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 778316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 779316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 780316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 781316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 782316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 783316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 784316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 785316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 786316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 787316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 788316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 789316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 790316485Sdavidcs#define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 791316485Sdavidcs __le32 psn_and_rxmit_id_echo /* reg0 */; 792316485Sdavidcs __le32 reg1 /* reg1 */; 793316485Sdavidcs __le32 reg2 /* reg2 */; 794316485Sdavidcs __le32 reg3 /* reg3 */; 795316485Sdavidcs __le32 reg4 /* reg4 */; 796316485Sdavidcs __le32 reg5 /* reg5 */; 797316485Sdavidcs __le32 reg6 /* reg6 */; 798316485Sdavidcs __le32 reg7 /* reg7 */; 799316485Sdavidcs __le32 reg8 /* reg8 */; 800316485Sdavidcs u8 tx_async_error_type /* byte2 */; 801316485Sdavidcs u8 byte3 /* byte3 */; 802316485Sdavidcs __le16 rq_cons /* word0 */; 803316485Sdavidcs u8 byte4 /* byte4 */; 804316485Sdavidcs u8 byte5 /* byte5 */; 805316485Sdavidcs __le16 rq_prod /* word1 */; 806316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 807316485Sdavidcs __le16 irq_cons /* word3 */; 808316485Sdavidcs __le32 num_invlidated_mw /* reg9 */; 809316485Sdavidcs __le32 reg10 /* reg10 */; 810316485Sdavidcs}; 811316485Sdavidcs 812316485Sdavidcs 813316485Sdavidcsstruct e4_ustorm_roce_req_conn_ag_ctx 814316485Sdavidcs{ 815316485Sdavidcs u8 byte0 /* cdu_validation */; 816316485Sdavidcs u8 byte1 /* state */; 817316485Sdavidcs u8 flags0; 818316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 819316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 820316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 821316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 822316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 823316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 824316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 825316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 826316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 827316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 828316485Sdavidcs u8 flags1; 829316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 830316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 831316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 832316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 833316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 834316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 835316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 836316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 837316485Sdavidcs u8 flags2; 838316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 839316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 840316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 841316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 842316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 843316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 844316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 845316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 846316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 847316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 848316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 849316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 850316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 851316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 852316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 853316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 854316485Sdavidcs u8 flags3; 855316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 856316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 857316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 858316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 859316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 860316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 861316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 862316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 863316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 864316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 865316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 866316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 867316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 868316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 869316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 870316485Sdavidcs#define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 871316485Sdavidcs u8 byte2 /* byte2 */; 872316485Sdavidcs u8 byte3 /* byte3 */; 873316485Sdavidcs __le16 word0 /* conn_dpi */; 874316485Sdavidcs __le16 word1 /* word1 */; 875316485Sdavidcs __le32 reg0 /* reg0 */; 876316485Sdavidcs __le32 reg1 /* reg1 */; 877316485Sdavidcs __le32 reg2 /* reg2 */; 878316485Sdavidcs __le32 reg3 /* reg3 */; 879316485Sdavidcs __le16 word2 /* word2 */; 880316485Sdavidcs __le16 word3 /* word3 */; 881316485Sdavidcs}; 882316485Sdavidcs 883316485Sdavidcs 884316485Sdavidcsstruct e4_ustorm_roce_resp_conn_ag_ctx 885316485Sdavidcs{ 886316485Sdavidcs u8 byte0 /* cdu_validation */; 887316485Sdavidcs u8 byte1 /* state */; 888316485Sdavidcs u8 flags0; 889316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 890316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 891316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 892316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 893316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 894316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 895316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 896316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 897316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 898316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 899316485Sdavidcs u8 flags1; 900316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 901316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 902316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 903316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 904316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 905316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 906316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 907316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 908316485Sdavidcs u8 flags2; 909316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 910316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 911316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 912316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 913316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 914316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 915316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 916316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 917316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 918316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 919316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 920316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 921316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 922316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 923316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 924316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 925316485Sdavidcs u8 flags3; 926316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 927316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 928316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 929316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 930316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 931316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 932316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 933316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 934316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 935316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 936316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 937316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 938316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 939316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 940316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 941316485Sdavidcs#define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 942316485Sdavidcs u8 byte2 /* byte2 */; 943316485Sdavidcs u8 byte3 /* byte3 */; 944316485Sdavidcs __le16 word0 /* conn_dpi */; 945316485Sdavidcs __le16 word1 /* word1 */; 946316485Sdavidcs __le32 reg0 /* reg0 */; 947316485Sdavidcs __le32 reg1 /* reg1 */; 948316485Sdavidcs __le32 reg2 /* reg2 */; 949316485Sdavidcs __le32 reg3 /* reg3 */; 950316485Sdavidcs __le16 word2 /* word2 */; 951316485Sdavidcs __le16 word3 /* word3 */; 952316485Sdavidcs}; 953316485Sdavidcs 954316485Sdavidcs 955316485Sdavidcsstruct e4_xstorm_roce_req_conn_ag_ctx 956316485Sdavidcs{ 957316485Sdavidcs u8 reserved0 /* cdu_validation */; 958316485Sdavidcs u8 state /* state */; 959316485Sdavidcs u8 flags0; 960316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 961316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 962316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 963316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 964316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 965316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 966316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 967316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 968316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 969316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 970316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 971316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 972316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 973316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 974316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 975316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 976316485Sdavidcs u8 flags1; 977316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 978316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 979316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 980316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 981316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 982316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 983316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 984316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 985316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 986316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 987316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 988316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 989316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 990316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 991316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 992316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 993316485Sdavidcs u8 flags2; 994316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 995316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 996316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 997316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 998316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 999316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 1000316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1001316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 1002316485Sdavidcs u8 flags3; 1003316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1004316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 1005316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1006316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1007316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1008316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 1009316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1010316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1011316485Sdavidcs u8 flags4; 1012316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1013316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 1014316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1015316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 1016316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1017316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 1018316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1019316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 1020316485Sdavidcs u8 flags5; 1021316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1022316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 1023316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1024316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 1025316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1026316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 1027316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1028316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 1029316485Sdavidcs u8 flags6; 1030316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1031316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 1032316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1033316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 1034316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1035316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 1036316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1037316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 1038316485Sdavidcs u8 flags7; 1039316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1040316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 1041316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1042316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 1043316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1044316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1045316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1046316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 1047316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1048316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 1049316485Sdavidcs u8 flags8; 1050316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1051316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 1052316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1053316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 1054316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1055316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 1056316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1057316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1058316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1059316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 1060316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1061316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1062316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1063316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 1064316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1065316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 1066316485Sdavidcs u8 flags9; 1067316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1068316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 1069316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1070316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 1071316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1072316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 1073316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1074316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 1075316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1076316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 1077316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1078316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 1079316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1080316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 1081316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1082316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 1083316485Sdavidcs u8 flags10; 1084316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1085316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 1086316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1087316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 1088316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1089316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 1090316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1091316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 1092316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1093316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1094316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1095316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 1096316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1097316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 1098316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1099316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 1100316485Sdavidcs u8 flags11; 1101316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1102316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 1103316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1104316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 1105316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1106316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 1107316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1108316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 1109316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1110316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 1111316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1112316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 1113316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1114316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1115316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1116316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 1117316485Sdavidcs u8 flags12; 1118316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1119316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 1120316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1121316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 1122316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1123316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1124316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1125316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1126316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1127316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 1128316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1129316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 1130316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1131316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 1132316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1133316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 1134316485Sdavidcs u8 flags13; 1135316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1136316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 1137316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1138316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 1139316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1140316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1141316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1142316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1143316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1144316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1145316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1146316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1147316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1148316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1149316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1150316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1151316485Sdavidcs u8 flags14; 1152316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1153316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 1154316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1155316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 1156316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1157316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1158316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1159316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 1160316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1161316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1162316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1163316485Sdavidcs#define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 1164316485Sdavidcs u8 byte2 /* byte2 */; 1165316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 1166316485Sdavidcs __le16 word1 /* physical_q1 */; 1167316485Sdavidcs __le16 sq_cmp_cons /* physical_q2 */; 1168316485Sdavidcs __le16 sq_cons /* word3 */; 1169316485Sdavidcs __le16 sq_prod /* word4 */; 1170316485Sdavidcs __le16 word5 /* word5 */; 1171316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1172316485Sdavidcs u8 byte3 /* byte3 */; 1173316485Sdavidcs u8 byte4 /* byte4 */; 1174316485Sdavidcs u8 byte5 /* byte5 */; 1175316485Sdavidcs u8 byte6 /* byte6 */; 1176316485Sdavidcs __le32 lsn /* reg0 */; 1177316485Sdavidcs __le32 ssn /* reg1 */; 1178316485Sdavidcs __le32 snd_una_psn /* reg2 */; 1179316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 1180316485Sdavidcs __le32 reg4 /* reg4 */; 1181316485Sdavidcs __le32 orq_cons_th /* cf_array0 */; 1182316485Sdavidcs __le32 orq_cons /* cf_array1 */; 1183316485Sdavidcs}; 1184316485Sdavidcs 1185316485Sdavidcs 1186316485Sdavidcsstruct e4_xstorm_roce_resp_conn_ag_ctx 1187316485Sdavidcs{ 1188316485Sdavidcs u8 reserved0 /* cdu_validation */; 1189316485Sdavidcs u8 state /* state */; 1190316485Sdavidcs u8 flags0; 1191316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1192316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1193316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1194316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 1195316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1196316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 1197316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1198316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1199316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 1200316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 1201316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 1202316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 1203316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1204316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 1205316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1206316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 1207316485Sdavidcs u8 flags1; 1208316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1209316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 1210316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1211316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 1212316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1213316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 1214316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1215316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 1216316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1217316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 1218316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1219316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 1220316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 1221316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 1222316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1223316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1224316485Sdavidcs u8 flags2; 1225316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1226316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 1227316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1228316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 1229316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1230316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 1231316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1232316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 1233316485Sdavidcs u8 flags3; 1234316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 1235316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 1236316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1237316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 1238316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 1239316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 1240316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1241316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1242316485Sdavidcs u8 flags4; 1243316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1244316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 1245316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1246316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 1247316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1248316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 1249316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1250316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 1251316485Sdavidcs u8 flags5; 1252316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1253316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 1254316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1255316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 1256316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1257316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 1258316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1259316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 1260316485Sdavidcs u8 flags6; 1261316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1262316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 1263316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1264316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 1265316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1266316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 1267316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1268316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 1269316485Sdavidcs u8 flags7; 1270316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1271316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 1272316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1273316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 1274316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1275316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1276316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1277316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 1278316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1279316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 1280316485Sdavidcs u8 flags8; 1281316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1282316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 1283316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1284316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 1285316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 1286316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 1287316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1288316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 1289316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 1290316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 1291316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1292316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1293316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1294316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 1295316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1296316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 1297316485Sdavidcs u8 flags9; 1298316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1299316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 1300316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1301316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 1302316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1303316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 1304316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1305316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 1306316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1307316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 1308316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1309316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 1310316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1311316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 1312316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1313316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 1314316485Sdavidcs u8 flags10; 1315316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1316316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 1317316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1318316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 1319316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1320316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 1321316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1322316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 1323316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1324316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1325316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1326316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 1327316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1328316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 1329316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1330316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 1331316485Sdavidcs u8 flags11; 1332316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1333316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 1334316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1335316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 1336316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1337316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 1338316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1339316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 1340316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1341316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 1342316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1343316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 1344316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1345316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1346316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1347316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 1348316485Sdavidcs u8 flags12; 1349337517Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule10en */ 1350337517Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 1351337517Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1352337517Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 1353316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1354316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1355316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1356316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1357316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1358316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 1359316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1360316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 1361316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1362316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 1363316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1364316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 1365316485Sdavidcs u8 flags13; 1366316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1367316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 1368316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1369316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 1370316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1371316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1372316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1373316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1374316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1375316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1376316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1377316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1378316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1379316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1380316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1381316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1382316485Sdavidcs u8 flags14; 1383316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1384316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 1385316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1386316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 1387316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1388316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 1389316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1390316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 1391316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1392316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 1393316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1394316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 1395316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1396316485Sdavidcs#define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 1397316485Sdavidcs u8 byte2 /* byte2 */; 1398316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 1399337517Sdavidcs __le16 irq_prod_shadow /* physical_q1 */; 1400337517Sdavidcs __le16 word2 /* physical_q2 */; 1401337517Sdavidcs __le16 irq_cons /* word3 */; 1402337517Sdavidcs __le16 irq_prod /* word4 */; 1403316485Sdavidcs __le16 e5_reserved1 /* word5 */; 1404337517Sdavidcs __le16 conn_dpi /* conn_dpi */; 1405316485Sdavidcs u8 rxmit_opcode /* byte3 */; 1406316485Sdavidcs u8 byte4 /* byte4 */; 1407316485Sdavidcs u8 byte5 /* byte5 */; 1408316485Sdavidcs u8 byte6 /* byte6 */; 1409316485Sdavidcs __le32 rxmit_psn_and_id /* reg0 */; 1410316485Sdavidcs __le32 rxmit_bytes_length /* reg1 */; 1411316485Sdavidcs __le32 psn /* reg2 */; 1412316485Sdavidcs __le32 reg3 /* reg3 */; 1413316485Sdavidcs __le32 reg4 /* reg4 */; 1414316485Sdavidcs __le32 reg5 /* cf_array0 */; 1415316485Sdavidcs __le32 msn_and_syndrome /* cf_array1 */; 1416316485Sdavidcs}; 1417316485Sdavidcs 1418316485Sdavidcs 1419316485Sdavidcsstruct e4_ystorm_roce_req_conn_ag_ctx 1420316485Sdavidcs{ 1421316485Sdavidcs u8 byte0 /* cdu_validation */; 1422316485Sdavidcs u8 byte1 /* state */; 1423316485Sdavidcs u8 flags0; 1424316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1425316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1426316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1427316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1428316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1429316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1430316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1431316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1432316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1433316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1434316485Sdavidcs u8 flags1; 1435316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1436316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1437316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1438316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1439316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1440316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1441316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1442316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1443316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1444316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1445316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1446316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1447316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1448316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1449316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1450316485Sdavidcs#define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1451316485Sdavidcs u8 byte2 /* byte2 */; 1452316485Sdavidcs u8 byte3 /* byte3 */; 1453316485Sdavidcs __le16 word0 /* word0 */; 1454316485Sdavidcs __le32 reg0 /* reg0 */; 1455316485Sdavidcs __le32 reg1 /* reg1 */; 1456316485Sdavidcs __le16 word1 /* word1 */; 1457316485Sdavidcs __le16 word2 /* word2 */; 1458316485Sdavidcs __le16 word3 /* word3 */; 1459316485Sdavidcs __le16 word4 /* word4 */; 1460316485Sdavidcs __le32 reg2 /* reg2 */; 1461316485Sdavidcs __le32 reg3 /* reg3 */; 1462316485Sdavidcs}; 1463316485Sdavidcs 1464316485Sdavidcs 1465316485Sdavidcsstruct e4_ystorm_roce_resp_conn_ag_ctx 1466316485Sdavidcs{ 1467316485Sdavidcs u8 byte0 /* cdu_validation */; 1468316485Sdavidcs u8 byte1 /* state */; 1469316485Sdavidcs u8 flags0; 1470316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1471316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1472316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1473316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1474316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1475316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1476316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1477316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1478316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1479316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1480316485Sdavidcs u8 flags1; 1481316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1482316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1483316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1484316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1485316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1486316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1487316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1488316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1489316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1490316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1491316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1492316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1493316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1494316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1495316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1496316485Sdavidcs#define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1497316485Sdavidcs u8 byte2 /* byte2 */; 1498316485Sdavidcs u8 byte3 /* byte3 */; 1499316485Sdavidcs __le16 word0 /* word0 */; 1500316485Sdavidcs __le32 reg0 /* reg0 */; 1501316485Sdavidcs __le32 reg1 /* reg1 */; 1502316485Sdavidcs __le16 word1 /* word1 */; 1503316485Sdavidcs __le16 word2 /* word2 */; 1504316485Sdavidcs __le16 word3 /* word3 */; 1505316485Sdavidcs __le16 word4 /* word4 */; 1506316485Sdavidcs __le32 reg2 /* reg2 */; 1507316485Sdavidcs __le32 reg3 /* reg3 */; 1508316485Sdavidcs}; 1509316485Sdavidcs 1510316485Sdavidcs 1511316485Sdavidcsstruct E5XstormRoceConnAgCtxDqExtLdPart 1512316485Sdavidcs{ 1513316485Sdavidcs u8 reserved0 /* cdu_validation */; 1514316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 1515316485Sdavidcs u8 flags0; 1516316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1517316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 1518316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 1519316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 1520316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 1521316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 1522316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1523316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 1524316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 /* bit4 */ 1525316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 1526316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 /* cf_array_active */ 1527316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 1528316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 /* bit6 */ 1529316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 1530316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 /* bit7 */ 1531316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 1532316485Sdavidcs u8 flags1; 1533316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 /* bit8 */ 1534316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 1535316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 /* bit9 */ 1536316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 1537316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 1538316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 1539316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 1540316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 1541316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 1542316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 1543316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 /* bit13 */ 1544316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 1545316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_MASK 0x1 /* bit14 */ 1546316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ERROR_STATE_SHIFT 6 1547316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1548316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 1549316485Sdavidcs u8 flags2; 1550316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 1551316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 1552316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 1553316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 1554316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 1555316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 1556316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 1557316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 1558316485Sdavidcs u8 flags3; 1559316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 1560316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_SHIFT 0 1561316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_MASK 0x3 /* cf5 */ 1562316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_SHIFT 2 1563316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 1564316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_SHIFT 4 1565316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1566316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 1567316485Sdavidcs u8 flags4; 1568316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 1569316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 1570316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 1571316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 1572316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 1573316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 1574316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 1575316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 1576316485Sdavidcs u8 flags5; 1577316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 1578316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 1579316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 1580316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 1581316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 1582316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FMR_ENDED_CF_SHIFT 4 1583316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 1584316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 1585316485Sdavidcs u8 flags6; 1586316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 1587316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 1588316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 1589316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 1590316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 1591316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 1592316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 1593316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 1594316485Sdavidcs u8 flags7; 1595316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 1596316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 1597316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 1598316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 1599316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 1600316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 1601316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 1602316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 1603316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 1604316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 1605316485Sdavidcs u8 flags8; 1606316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 1607316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 1608316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 1609316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 1610316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 1611316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_FLUSH_CF_EN_SHIFT 2 1612316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 1613316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RX_ERROR_CF_EN_SHIFT 3 1614316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 1615316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SND_RXMIT_CF_EN_SHIFT 4 1616316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1617316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 1618316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 1619316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 1620316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 1621316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 1622316485Sdavidcs u8 flags9; 1623316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 1624316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 1625316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 1626316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 1627316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 1628316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 1629316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 1630316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 1631316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 1632316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_FME_ENDED_CF_EN_SHIFT 4 1633316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 1634316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 1635316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 1636316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 1637316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1638316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 1639316485Sdavidcs u8 flags10; 1640316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 1641316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 1642316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 1643316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 1644316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 1645316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 1646316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 1647316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 1648316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1649316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 1650316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 1651316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 1652316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 1653316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 1654316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 1655316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 1656316485Sdavidcs u8 flags11; 1657316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 1658316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 1659316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 1660316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 1661316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 1662316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 1663316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 1664316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 1665316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 1666316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 1667316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 1668316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E2E_CREDIT_RULE_EN_SHIFT 5 1669316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 1670316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 1671316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 1672316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 1673316485Sdavidcs u8 flags12; 1674316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_MASK 0x1 /* rule10en */ 1675316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_SQ_PROD_EN_SHIFT 0 1676316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 1677316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 1678316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 1679316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 1680316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 1681316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 1682316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 1683316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_INV_FENCE_RULE_EN_SHIFT 4 1684316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 1685316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 1686316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 1687316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ORQ_FENCE_RULE_EN_SHIFT 6 1688316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 1689316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_MAX_ORD_RULE_EN_SHIFT 7 1690316485Sdavidcs u8 flags13; 1691316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 1692316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 1693316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 1694316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 1695316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 1696316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 1697316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 1698316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1699316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1700316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1701316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1702316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1703316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1704316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1705316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1706316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1707316485Sdavidcs u8 flags14; 1708316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 1709316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_FLAG_SHIFT 0 1710316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 1711316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 1712316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1713316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 1714316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 1715316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 1716316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1717316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1718316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 1719316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 1720316485Sdavidcs u8 byte2 /* byte2 */; 1721316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 1722316485Sdavidcs __le16 word1 /* physical_q1 */; 1723316485Sdavidcs __le16 sq_cmp_cons /* physical_q2 */; 1724316485Sdavidcs __le16 sq_cons /* word3 */; 1725316485Sdavidcs __le16 sq_prod /* word4 */; 1726316485Sdavidcs __le16 word5 /* word5 */; 1727316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1728316485Sdavidcs u8 byte3 /* byte3 */; 1729316485Sdavidcs u8 byte4 /* byte4 */; 1730316485Sdavidcs u8 byte5 /* byte5 */; 1731316485Sdavidcs u8 byte6 /* byte6 */; 1732316485Sdavidcs __le32 lsn /* reg0 */; 1733316485Sdavidcs __le32 ssn /* reg1 */; 1734316485Sdavidcs __le32 snd_una_psn /* reg2 */; 1735316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 1736316485Sdavidcs __le32 reg4 /* reg4 */; 1737316485Sdavidcs __le32 orq_cons_th /* cf_array0 */; 1738316485Sdavidcs __le32 orq_cons /* cf_array1 */; 1739316485Sdavidcs u8 flags15; 1740316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_MASK 0x1 /* bit22 */ 1741316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED1_SHIFT 0 1742316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_MASK 0x1 /* bit23 */ 1743316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED2_SHIFT 1 1744316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_MASK 0x1 /* bit24 */ 1745316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED3_SHIFT 2 1746316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_MASK 0x3 /* cf24 */ 1747316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED4_SHIFT 3 1748316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_MASK 0x1 /* cf24en */ 1749316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED5_SHIFT 5 1750316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_MASK 0x1 /* rule26en */ 1751316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED6_SHIFT 6 1752316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_MASK 0x1 /* rule27en */ 1753316485Sdavidcs#define E5XSTORMROCECONNAGCTXDQEXTLDPART_E4_RESERVED7_SHIFT 7 1754316485Sdavidcs u8 byte7 /* byte7 */; 1755316485Sdavidcs __le16 word7 /* word7 */; 1756316485Sdavidcs __le16 word8 /* word8 */; 1757316485Sdavidcs __le16 word9 /* word9 */; 1758316485Sdavidcs __le16 word10 /* word10 */; 1759316485Sdavidcs __le16 tx_rdma_edpm_usg_cnt /* word11 */; 1760316485Sdavidcs __le32 reg7 /* reg7 */; 1761316485Sdavidcs __le32 reg8 /* reg8 */; 1762316485Sdavidcs __le32 reg9 /* reg9 */; 1763316485Sdavidcs u8 byte8 /* byte8 */; 1764316485Sdavidcs u8 byte9 /* byte9 */; 1765316485Sdavidcs u8 byte10 /* byte10 */; 1766316485Sdavidcs u8 byte11 /* byte11 */; 1767316485Sdavidcs u8 byte12 /* byte12 */; 1768316485Sdavidcs u8 byte13 /* byte13 */; 1769316485Sdavidcs u8 byte14 /* byte14 */; 1770316485Sdavidcs u8 byte15 /* byte15 */; 1771316485Sdavidcs __le32 reg10 /* reg10 */; 1772316485Sdavidcs __le32 reg11 /* reg11 */; 1773316485Sdavidcs __le32 reg12 /* reg12 */; 1774316485Sdavidcs __le32 reg13 /* reg13 */; 1775316485Sdavidcs}; 1776316485Sdavidcs 1777316485Sdavidcs 1778316485Sdavidcsstruct e5_mstorm_roce_req_conn_ag_ctx 1779316485Sdavidcs{ 1780316485Sdavidcs u8 byte0 /* cdu_validation */; 1781316485Sdavidcs u8 byte1 /* state_and_core_id */; 1782316485Sdavidcs u8 flags0; 1783316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1784316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 1785316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1786316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 1787316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1788316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 1789316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1790316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 1791316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1792316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 1793316485Sdavidcs u8 flags1; 1794316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1795316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 1796316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1797316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 1798316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1799316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 1800316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1801316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 1802316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1803316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 1804316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1805316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 1806316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1807316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 1808316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1809316485Sdavidcs#define E5_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 1810316485Sdavidcs __le16 word0 /* word0 */; 1811316485Sdavidcs __le16 word1 /* word1 */; 1812316485Sdavidcs __le32 reg0 /* reg0 */; 1813316485Sdavidcs __le32 reg1 /* reg1 */; 1814316485Sdavidcs}; 1815316485Sdavidcs 1816316485Sdavidcs 1817316485Sdavidcsstruct e5_mstorm_roce_resp_conn_ag_ctx 1818316485Sdavidcs{ 1819316485Sdavidcs u8 byte0 /* cdu_validation */; 1820316485Sdavidcs u8 byte1 /* state_and_core_id */; 1821316485Sdavidcs u8 flags0; 1822316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1823316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 1824316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1825316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 1826316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1827316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 1828316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1829316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 1830316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1831316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 1832316485Sdavidcs u8 flags1; 1833316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1834316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 1835316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1836316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 1837316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1838316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 1839316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1840316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 1841316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1842316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 1843316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1844316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 1845316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1846316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 1847316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1848316485Sdavidcs#define E5_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 1849316485Sdavidcs __le16 word0 /* word0 */; 1850316485Sdavidcs __le16 word1 /* word1 */; 1851316485Sdavidcs __le32 reg0 /* reg0 */; 1852316485Sdavidcs __le32 reg1 /* reg1 */; 1853316485Sdavidcs}; 1854316485Sdavidcs 1855316485Sdavidcs 1856316485Sdavidcsstruct e5_tstorm_roce_req_conn_ag_ctx 1857316485Sdavidcs{ 1858316485Sdavidcs u8 reserved0 /* cdu_validation */; 1859316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 1860316485Sdavidcs u8 flags0; 1861316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1862316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1863316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 /* exist_in_qm1 */ 1864316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 1865316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 /* bit2 */ 1866316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 1867316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1868316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 1869316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1870316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1871316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 /* bit5 */ 1872316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 1873316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0cf */ 1874316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 1875316485Sdavidcs u8 flags1; 1876316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1877316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 1878316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 /* timer2cf */ 1879316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 1880316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1881316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1882316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1883316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1884316485Sdavidcs u8 flags2; 1885316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1886316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1887316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 /* cf6 */ 1888316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 1889316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 /* cf7 */ 1890316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 1891316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 /* cf8 */ 1892316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 1893316485Sdavidcs u8 flags3; 1894316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 /* cf9 */ 1895316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 1896316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 /* cf10 */ 1897316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 1898316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1899316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 1900316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1901316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 1902316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 /* cf2en */ 1903316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 1904316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1905316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1906316485Sdavidcs u8 flags4; 1907316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1908316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1909316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1910316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1911316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 /* cf6en */ 1912316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 1913316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 /* cf7en */ 1914316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 1915316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 /* cf8en */ 1916316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 1917316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 /* cf9en */ 1918316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 1919316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 /* cf10en */ 1920316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 1921316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1922316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 1923316485Sdavidcs u8 flags5; 1924316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1925316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 1926316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1927316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 1928316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1929316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 1930316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1931316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 1932316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1933316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 1934316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 /* rule6en */ 1935316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 1936316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1937316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 1938316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1939316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 1940316485Sdavidcs u8 flags6; 1941316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1942316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1943316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1944316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1945316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1946316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1947316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1948316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1949316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1950316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1951316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1952316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1953316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1954316485Sdavidcs#define E5_TSTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1955316485Sdavidcs u8 tx_cqe_error_type /* byte2 */; 1956316485Sdavidcs __le16 snd_sq_cons_th /* word0 */; 1957316485Sdavidcs __le32 reg0 /* reg0 */; 1958316485Sdavidcs __le32 snd_nxt_psn /* reg1 */; 1959316485Sdavidcs __le32 snd_max_psn /* reg2 */; 1960316485Sdavidcs __le32 orq_prod /* reg3 */; 1961316485Sdavidcs __le32 reg4 /* reg4 */; 1962316485Sdavidcs __le32 reg5 /* reg5 */; 1963316485Sdavidcs __le32 reg6 /* reg6 */; 1964316485Sdavidcs __le32 reg7 /* reg7 */; 1965316485Sdavidcs __le32 reg8 /* reg8 */; 1966316485Sdavidcs u8 orq_cache_idx /* byte3 */; 1967316485Sdavidcs u8 byte4 /* byte4 */; 1968316485Sdavidcs u8 byte5 /* byte5 */; 1969316485Sdavidcs u8 e4_reserved8 /* byte6 */; 1970316485Sdavidcs __le16 snd_sq_cons /* word1 */; 1971316485Sdavidcs __le16 word2 /* conn_dpi */; 1972316485Sdavidcs __le32 reg9 /* reg9 */; 1973316485Sdavidcs __le16 word3 /* word3 */; 1974316485Sdavidcs __le16 e4_reserved9 /* word4 */; 1975316485Sdavidcs}; 1976316485Sdavidcs 1977316485Sdavidcs 1978316485Sdavidcsstruct e5_tstorm_roce_resp_conn_ag_ctx 1979316485Sdavidcs{ 1980316485Sdavidcs u8 byte0 /* cdu_validation */; 1981316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 1982316485Sdavidcs u8 flags0; 1983337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1984337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1985337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 /* exist_in_qm1 */ 1986337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 1987337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1988337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 1989337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1990337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 1991337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit4 */ 1992337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 1993337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1994337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 1995337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1996337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 1997316485Sdavidcs u8 flags1; 1998337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* timer1cf */ 1999337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 2000337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 /* timer2cf */ 2001337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 2002337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2003337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 2004337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 2005337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2006316485Sdavidcs u8 flags2; 2007337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 2008337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 2009337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2010337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 2011337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2012337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 2013337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2014337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 2015316485Sdavidcs u8 flags3; 2016337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2017337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 2018337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2019337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 2020337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2021337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 2022337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf1en */ 2023337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 2024337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 /* cf2en */ 2025337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 2026337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2027337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 2028316485Sdavidcs u8 flags4; 2029337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 2030337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 2031337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 2032337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 2033337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2034337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 2035337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2036337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 2037337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2038337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 2039337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2040337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 2041337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2042337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 2043337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2044337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2045316485Sdavidcs u8 flags5; 2046337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2047337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2048337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2049337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2050337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2051337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2052337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2053337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2054337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2055337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2056337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 /* rule6en */ 2057337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 2058337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2059337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2060337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2061337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2062316485Sdavidcs u8 flags6; 2063337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 2064337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2065337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 2066337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2067337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 2068337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2069337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 2070337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2071337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 2072337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2073337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 2074337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2075337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 2076337517Sdavidcs#define E5_TSTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2077316485Sdavidcs u8 tx_async_error_type /* byte2 */; 2078316485Sdavidcs __le16 rq_cons /* word0 */; 2079316485Sdavidcs __le32 psn_and_rxmit_id_echo /* reg0 */; 2080316485Sdavidcs __le32 reg1 /* reg1 */; 2081316485Sdavidcs __le32 reg2 /* reg2 */; 2082316485Sdavidcs __le32 reg3 /* reg3 */; 2083316485Sdavidcs __le32 reg4 /* reg4 */; 2084316485Sdavidcs __le32 reg5 /* reg5 */; 2085316485Sdavidcs __le32 reg6 /* reg6 */; 2086316485Sdavidcs __le32 reg7 /* reg7 */; 2087316485Sdavidcs __le32 reg8 /* reg8 */; 2088316485Sdavidcs u8 byte3 /* byte3 */; 2089316485Sdavidcs u8 byte4 /* byte4 */; 2090316485Sdavidcs u8 byte5 /* byte5 */; 2091316485Sdavidcs u8 e4_reserved8 /* byte6 */; 2092316485Sdavidcs __le16 rq_prod /* word1 */; 2093316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 2094316485Sdavidcs __le32 num_invlidated_mw /* reg9 */; 2095316485Sdavidcs __le16 irq_cons /* word3 */; 2096316485Sdavidcs __le16 e4_reserved9 /* word4 */; 2097316485Sdavidcs}; 2098316485Sdavidcs 2099316485Sdavidcs 2100316485Sdavidcsstruct e5_ustorm_roce_req_conn_ag_ctx 2101316485Sdavidcs{ 2102316485Sdavidcs u8 byte0 /* cdu_validation */; 2103316485Sdavidcs u8 byte1 /* state_and_core_id */; 2104316485Sdavidcs u8 flags0; 2105316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2106316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2107316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2108316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2109316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2110316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2111316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2112316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2113316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2114316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2115316485Sdavidcs u8 flags1; 2116316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2117316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 2118316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2119316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 2120316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2121316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 2122316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2123316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 2124316485Sdavidcs u8 flags2; 2125316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2126316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2127316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2128316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2129316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2130316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2131316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2132316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 2133316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2134316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 2135316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2136316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 2137316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2138316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 2139316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2140316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 2141316485Sdavidcs u8 flags3; 2142316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2143316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 2144316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2145316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 2146316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2147316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 2148316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2149316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 2150316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2151316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 2152316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2153316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 2154316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2155316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 2156316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2157316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 2158316485Sdavidcs u8 flags4; 2159316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2160316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2161316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2162316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2163316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2164316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2165316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2166316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2167316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2168316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2169316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2170316485Sdavidcs#define E5_USTORM_ROCE_REQ_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2171316485Sdavidcs u8 byte2 /* byte2 */; 2172316485Sdavidcs __le16 word0 /* conn_dpi */; 2173316485Sdavidcs __le16 word1 /* word1 */; 2174316485Sdavidcs __le32 reg0 /* reg0 */; 2175316485Sdavidcs __le32 reg1 /* reg1 */; 2176316485Sdavidcs __le32 reg2 /* reg2 */; 2177316485Sdavidcs __le32 reg3 /* reg3 */; 2178316485Sdavidcs __le16 word2 /* word2 */; 2179316485Sdavidcs __le16 word3 /* word3 */; 2180316485Sdavidcs}; 2181316485Sdavidcs 2182316485Sdavidcs 2183316485Sdavidcsstruct e5_ustorm_roce_resp_conn_ag_ctx 2184316485Sdavidcs{ 2185316485Sdavidcs u8 byte0 /* cdu_validation */; 2186316485Sdavidcs u8 byte1 /* state_and_core_id */; 2187316485Sdavidcs u8 flags0; 2188316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2189316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2190316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2191316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2192316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2193316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2194316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2195316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2196316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2197316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2198316485Sdavidcs u8 flags1; 2199316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2200316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 2201316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2202316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 2203316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2204316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 2205316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2206316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 2207316485Sdavidcs u8 flags2; 2208316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2209316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2210316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2211316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2212316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2213316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2214316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2215316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 2216316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2217316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 2218316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2219316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 2220316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2221316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 2222316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2223316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 2224316485Sdavidcs u8 flags3; 2225316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2226316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 2227316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2228316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 2229316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2230316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 2231316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2232316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 2233316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2234316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 2235316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2236316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 2237316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2238316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 2239316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2240316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 2241316485Sdavidcs u8 flags4; 2242316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2243316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2244316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2245316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2246316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2247316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2248316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2249316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2250316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2251316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2252316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2253316485Sdavidcs#define E5_USTORM_ROCE_RESP_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2254316485Sdavidcs u8 byte2 /* byte2 */; 2255316485Sdavidcs __le16 word0 /* conn_dpi */; 2256316485Sdavidcs __le16 word1 /* word1 */; 2257316485Sdavidcs __le32 reg0 /* reg0 */; 2258316485Sdavidcs __le32 reg1 /* reg1 */; 2259316485Sdavidcs __le32 reg2 /* reg2 */; 2260316485Sdavidcs __le32 reg3 /* reg3 */; 2261316485Sdavidcs __le16 word2 /* word2 */; 2262316485Sdavidcs __le16 word3 /* word3 */; 2263316485Sdavidcs}; 2264316485Sdavidcs 2265316485Sdavidcs 2266316485Sdavidcsstruct e5_xstorm_roce_req_conn_ag_ctx 2267316485Sdavidcs{ 2268316485Sdavidcs u8 reserved0 /* cdu_validation */; 2269316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 2270316485Sdavidcs u8 flags0; 2271316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2272316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2273316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2274316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 2275316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2276316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 2277316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2278316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2279316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2280316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 2281316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2282316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 2283316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2284316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 2285316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2286316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 2287316485Sdavidcs u8 flags1; 2288316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2289316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 2290316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2291316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 2292316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2293316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 2294316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2295316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 2296316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2297316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 2298316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2299316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 2300316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2301316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2302316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2303316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2304316485Sdavidcs u8 flags2; 2305316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2306316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 2307316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2308316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 2309316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2310316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 2311316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2312316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 2313316485Sdavidcs u8 flags3; 2314316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf4 */ 2315316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 2316316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2317316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2318316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 /* cf6 */ 2319316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 2320316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2321316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2322316485Sdavidcs u8 flags4; 2323316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2324316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 2325316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2326316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 2327316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2328316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 2329316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2330316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 2331316485Sdavidcs u8 flags5; 2332316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2333316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 2334316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2335316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 2336316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 /* cf14 */ 2337316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 2338316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2339316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 2340316485Sdavidcs u8 flags6; 2341316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2342316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 2343316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2344316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 2345316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2346316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 2347316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2348316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 2349316485Sdavidcs u8 flags7; 2350316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2351316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 2352316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2353316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 2354316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2355316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2356316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2357316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 2358316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2359316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 2360316485Sdavidcs u8 flags8; 2361316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2362316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 2363316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2364316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 2365316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 /* cf4en */ 2366316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 2367316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2368316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2369316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 /* cf6en */ 2370316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 2371316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2372316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2373316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2374316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 2375316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2376316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 2377316485Sdavidcs u8 flags9; 2378316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2379316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 2380316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2381316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 2382316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2383316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 2384316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2385316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 2386316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 /* cf14en */ 2387316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 2388316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2389316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 2390316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2391316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 2392316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2393316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 2394316485Sdavidcs u8 flags10; 2395316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2396316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 2397316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2398316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 2399316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2400316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 2401316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2402316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 2403316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2404316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2405316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2406316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 2407316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2408316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 2409316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2410316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 2411316485Sdavidcs u8 flags11; 2412316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2413316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 2414316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2415316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 2416316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2417316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 2418316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2419316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 2420316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2421316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 2422316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 /* rule7en */ 2423316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 2424316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2425316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2426316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2427316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 2428316485Sdavidcs u8 flags12; 2429316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 /* rule10en */ 2430316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 2431316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2432316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 2433316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2434316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2435316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2436316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2437316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 /* rule14en */ 2438316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 2439316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2440316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 2441316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 /* rule16en */ 2442316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 2443316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 /* rule17en */ 2444316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 2445316485Sdavidcs u8 flags13; 2446316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2447316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 2448316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2449316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 2450316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2451316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2452316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2453316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2454316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2455316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2456316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2457316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2458316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2459316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2460316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2461316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2462316485Sdavidcs u8 flags14; 2463316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 /* bit16 */ 2464316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 2465316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2466316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 2467316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2468316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2469316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2470316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 2471316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2472316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2473316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2474316485Sdavidcs#define E5_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 2475316485Sdavidcs u8 byte2 /* byte2 */; 2476316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 2477316485Sdavidcs __le16 word1 /* physical_q1 */; 2478316485Sdavidcs __le16 sq_cmp_cons /* physical_q2 */; 2479316485Sdavidcs __le16 sq_cons /* word3 */; 2480316485Sdavidcs __le16 sq_prod /* word4 */; 2481316485Sdavidcs __le16 word5 /* word5 */; 2482316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 2483316485Sdavidcs u8 byte3 /* byte3 */; 2484316485Sdavidcs u8 byte4 /* byte4 */; 2485316485Sdavidcs u8 byte5 /* byte5 */; 2486316485Sdavidcs u8 byte6 /* byte6 */; 2487316485Sdavidcs __le32 lsn /* reg0 */; 2488316485Sdavidcs __le32 ssn /* reg1 */; 2489316485Sdavidcs __le32 snd_una_psn /* reg2 */; 2490316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 2491316485Sdavidcs __le32 reg4 /* reg4 */; 2492316485Sdavidcs __le32 orq_cons_th /* cf_array0 */; 2493316485Sdavidcs __le32 orq_cons /* cf_array1 */; 2494316485Sdavidcs}; 2495316485Sdavidcs 2496316485Sdavidcs 2497316485Sdavidcsstruct e5_xstorm_roce_resp_conn_ag_ctx 2498316485Sdavidcs{ 2499316485Sdavidcs u8 reserved0 /* cdu_validation */; 2500316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 2501316485Sdavidcs u8 flags0; 2502316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2503316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2504316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2505316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 2506316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2507316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 2508316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2509316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2510316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2511316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 2512316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2513316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 2514316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2515316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 2516316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2517316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 2518316485Sdavidcs u8 flags1; 2519316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2520316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 2521316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2522316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 2523316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 2524316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 2525316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2526316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 2527316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2528316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 2529316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2530316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 2531316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 /* bit14 */ 2532316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 2533316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 2534316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 2535316485Sdavidcs u8 flags2; 2536316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2537316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 2538316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2539316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 2540316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2541316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 2542316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2543316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 2544316485Sdavidcs u8 flags3; 2545316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 /* cf4 */ 2546316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 2547316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 /* cf5 */ 2548316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 2549316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 /* cf6 */ 2550316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 2551316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2552316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2553316485Sdavidcs u8 flags4; 2554316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2555316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 2556316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2557316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 2558316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2559316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 2560316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2561316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 2562316485Sdavidcs u8 flags5; 2563316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2564316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 2565316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2566316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 2567316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2568316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 2569316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2570316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 2571316485Sdavidcs u8 flags6; 2572316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2573316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 2574316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2575316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 2576316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2577316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 2578316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2579316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 2580316485Sdavidcs u8 flags7; 2581316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2582316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 2583316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2584316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 2585316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2586316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2587316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2588316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 2589316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2590316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 2591316485Sdavidcs u8 flags8; 2592316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2593316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 2594316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2595316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 2596316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 /* cf4en */ 2597316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 2598316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 /* cf5en */ 2599316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 2600316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 /* cf6en */ 2601316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 2602316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2603316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2604316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2605316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 2606316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2607316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 2608316485Sdavidcs u8 flags9; 2609316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2610316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 2611316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2612316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 2613316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2614316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 2615316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2616316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 2617316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2618316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 2619316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2620316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 2621316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2622316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 2623316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2624316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 2625316485Sdavidcs u8 flags10; 2626316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2627316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 2628316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2629316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 2630316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2631316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 2632316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2633316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 2634316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2635316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2636316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2637316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 2638316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2639316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 2640316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2641316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 2642316485Sdavidcs u8 flags11; 2643316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2644316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 2645316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2646316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 2647316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2648316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 2649316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2650316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 2651316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2652316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 2653316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2654316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 2655316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2656316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2657316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2658316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 2659316485Sdavidcs u8 flags12; 2660316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2661316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 2662316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 /* rule11en */ 2663316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 2664316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2665316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2666316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2667316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2668316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2669316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 2670316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2671316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 2672316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2673316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 2674316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2675316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 2676316485Sdavidcs u8 flags13; 2677316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2678316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 2679316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2680316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 2681316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2682316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2683316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2684316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2685316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2686316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2687316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2688316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2689316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2690316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2691316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2692316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2693316485Sdavidcs u8 flags14; 2694316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 2695316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 2696316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2697316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 2698316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 2699316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 2700316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 2701316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 2702316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 2703316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 2704316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 2705316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 2706316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2707316485Sdavidcs#define E5_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 2708316485Sdavidcs u8 byte2 /* byte2 */; 2709316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 2710316485Sdavidcs __le16 word1 /* physical_q1 */; 2711316485Sdavidcs __le16 irq_prod /* physical_q2 */; 2712316485Sdavidcs __le16 word3 /* word3 */; 2713316485Sdavidcs __le16 word4 /* word4 */; 2714316485Sdavidcs __le16 ack_cons /* word5 */; 2715316485Sdavidcs __le16 irq_cons /* conn_dpi */; 2716316485Sdavidcs u8 rxmit_opcode /* byte3 */; 2717316485Sdavidcs u8 byte4 /* byte4 */; 2718316485Sdavidcs u8 byte5 /* byte5 */; 2719316485Sdavidcs u8 byte6 /* byte6 */; 2720316485Sdavidcs __le32 rxmit_psn_and_id /* reg0 */; 2721316485Sdavidcs __le32 rxmit_bytes_length /* reg1 */; 2722316485Sdavidcs __le32 psn /* reg2 */; 2723316485Sdavidcs __le32 reg3 /* reg3 */; 2724316485Sdavidcs __le32 reg4 /* reg4 */; 2725316485Sdavidcs __le32 reg5 /* cf_array0 */; 2726316485Sdavidcs __le32 msn_and_syndrome /* cf_array1 */; 2727316485Sdavidcs}; 2728316485Sdavidcs 2729316485Sdavidcs 2730316485Sdavidcsstruct e5_ystorm_roce_req_conn_ag_ctx 2731316485Sdavidcs{ 2732316485Sdavidcs u8 byte0 /* cdu_validation */; 2733316485Sdavidcs u8 byte1 /* state_and_core_id */; 2734316485Sdavidcs u8 flags0; 2735316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2736316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 2737316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2738316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 2739316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2740316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 2741316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2742316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 2743316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2744316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 2745316485Sdavidcs u8 flags1; 2746316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2747316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 2748316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2749316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 2750316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2751316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 2752316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2753316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 2754316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2755316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 2756316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2757316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 2758316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2759316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 2760316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2761316485Sdavidcs#define E5_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 2762316485Sdavidcs u8 byte2 /* byte2 */; 2763316485Sdavidcs u8 byte3 /* byte3 */; 2764316485Sdavidcs __le16 word0 /* word0 */; 2765316485Sdavidcs __le32 reg0 /* reg0 */; 2766316485Sdavidcs __le32 reg1 /* reg1 */; 2767316485Sdavidcs __le16 word1 /* word1 */; 2768316485Sdavidcs __le16 word2 /* word2 */; 2769316485Sdavidcs __le16 word3 /* word3 */; 2770316485Sdavidcs __le16 word4 /* word4 */; 2771316485Sdavidcs __le32 reg2 /* reg2 */; 2772316485Sdavidcs __le32 reg3 /* reg3 */; 2773316485Sdavidcs}; 2774316485Sdavidcs 2775316485Sdavidcs 2776316485Sdavidcsstruct e5_ystorm_roce_resp_conn_ag_ctx 2777316485Sdavidcs{ 2778316485Sdavidcs u8 byte0 /* cdu_validation */; 2779316485Sdavidcs u8 byte1 /* state_and_core_id */; 2780316485Sdavidcs u8 flags0; 2781316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2782316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 2783316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2784316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 2785316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2786316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 2787316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2788316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 2789316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2790316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 2791316485Sdavidcs u8 flags1; 2792316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2793316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 2794316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2795316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 2796316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2797316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 2798316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2799316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 2800316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2801316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 2802316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2803316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 2804316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2805316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 2806316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2807316485Sdavidcs#define E5_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 2808316485Sdavidcs u8 byte2 /* byte2 */; 2809316485Sdavidcs u8 byte3 /* byte3 */; 2810316485Sdavidcs __le16 word0 /* word0 */; 2811316485Sdavidcs __le32 reg0 /* reg0 */; 2812316485Sdavidcs __le32 reg1 /* reg1 */; 2813316485Sdavidcs __le16 word1 /* word1 */; 2814316485Sdavidcs __le16 word2 /* word2 */; 2815316485Sdavidcs __le16 word3 /* word3 */; 2816316485Sdavidcs __le16 word4 /* word4 */; 2817316485Sdavidcs __le32 reg2 /* reg2 */; 2818316485Sdavidcs __le32 reg3 /* reg3 */; 2819316485Sdavidcs}; 2820316485Sdavidcs 2821316485Sdavidcs 2822316485Sdavidcs/* 2823316485Sdavidcs * Roce doorbell data 2824316485Sdavidcs */ 2825316485Sdavidcsenum roce_flavor 2826316485Sdavidcs{ 2827316485Sdavidcs PLAIN_ROCE /* RoCE v1 */, 2828316485Sdavidcs RROCE_IPV4 /* RoCE v2 (Routable RoCE) over ipv4 */, 2829316485Sdavidcs RROCE_IPV6 /* RoCE v2 (Routable RoCE) over ipv6 */, 2830316485Sdavidcs MAX_ROCE_FLAVOR 2831316485Sdavidcs}; 2832316485Sdavidcs 2833316485Sdavidcs#endif /* __ECORE_HSI_ROCE__ */ 2834